Abstract: A digital-to-analog converter (DAC) for generating a high-precision analog output signal corresponding to a non-linear function, such as a sine function, of a digital input quantity, without the need for large numbers of precision current generators. Binary weighted current sources provide currents that, when selectively combined to provide a single output current, are approximately equivalent to the non-linear function of the digital input quantity, and an interpolation network provides an interpolation current that is added to the output current. The interpolation network may be selected to provide linear or non-linear interpolation between output current values. In other disclosed embodiments, multiple interpolation networks are used, either to provide different interpolation techniques for different ranges of input values, or to be connected effectively in series to provide for still greater accuracy without using additional current sources.

Abstract: The present invention relates to an apparatus and method for distributing electrical power from power substation circuits. The apparatus of the present invention is responsive to overcurrent conditions and selectively actuates a switching network so as to restore power to at least a portion of the users connected to the faulty circuit of the power distribution system.

Abstract: A multi-code-book variable length decoder for decoding an input bit stream containing a plurality of variable length code words includes a plurality of individual variable length decoders and a controller. Each of the individual variable length decoders receives the input bit stream and decodes the input bit stream according to a different respective code book. The controller receives the input bit stream and, for each successive code word contained in the input bit stream, selects a correct one of the plurality of individual variable length decoders for decoding that code word.

Abstract: The disclosure concerns a so-called "auto-zeroing" comparator of two analog input voltages to be compared, and an analog-to-digital converter using a set of auto-zeroing comparators enabling the number of comparators required for an analog-to-digital conversion to be reduced. The main originality of the invention is that this comparator includes a second stage constituted by an inverter function provided in such a way that only a first transistor is controlled on its gate by the previous stage, a second transistor having its gate and drain short-circuited by a switch during the auto-zeroing phase, and a third transistor used as a capacitor and connected to the gate of said second transistor and also to the supply voltage. The present invention is applicable in particular to all types of CMOS multi-comparison ADCs using at least one "auto-zeroing" comparator.

Abstract: An overvoltage protection apparatus is used with a pair of telephone or communications TIP/A and RING/B lines including voltage clamping circuitry for clamping voltage signals on the lines at a predetermined voltage potential. The voltage clamping circuitry includes a pair of voltage clamping devices connected in series between the TIP/A and RING/B lines and a third voltage clamping device connected between a junction connection of the pair of the voltage clamping devices and a ground potential connection and current limiting devices for limiting current flow in the lines. The predetermined voltage potential exceeds a primary alternating current (AC) power line peak value by a set tolerance value.

Abstract: Methods and apparatus for an analog-to-digital converter (ADC) with reduced comparator-hysteresis effects. One embodiment uses a charge-redistribution ADC. One method performs an initial coarse analog-to-digital conversion to avoid overdriving an analog voltage comparator. One such method includes a redundant capacitor in an array of charge-redistribution capacitors used in the ADC for sample-and-hold and successive-approximation functions. Another method performs a traditional initial successive-approximation analog-to-digital conversion, and then performs an additional conversion-step test based on the least-significant bit of the initial result to correct for comparator errors in the initial conversion.

Abstract: An analog voltage address decoder circuit and stackable voltage comparator circuit are provided. The address decoder circuit has a column decode comparator network made up of a first plurality of interconnected comparator circuits and a row decode comparator network made up of a second plurality of interconnected comparator circuits. The column decode comparator network compares a plurality of reference voltages with an analog input voltage so as to detect if the analog input voltage is within a bounded window. Likewise, the row decode comparator network compares an analog input voltage with a plurality of reference voltages to detect if the analog input voltage is within a bounded window. Detection within the proper bounded windows for the rows and columns produces a corresponding "high" binary output to a particular memory location for access thereto. The decode comparator networks use stackable voltage comparator circuits to perform the voltage window comparisons.

Abstract: A decoding method for tri-state read-only memory is disclosed herein. The cells of the tri-state memory are read the storage bits of all cells are combined to form a storage code. Each bit represents one of a first state, a second state and a third state. The storage code is first decoded to convert the storage code into an intermediate code. The intermediate code includes a plurality of conversion codes, each of which is one of a first code, a second code, and a third code corresponding respectively to the first, second, and third states. The intermediate code is further decoded into the binary output code. The resulting binary code has a greater number of bits than its corresponding storage code. Thus, the read-only memory, in accordance with the present invention, can store more than one bit of data in a single memory cell.

Abstract: Fault tolerant thermoelectric device circuit (18) is provided including a plurality of thermoelectric elements (19, 20, 21, and 22) and a plurality of secondary by-pass circuits (24, 25, 26, and 27) coupled in parallel with a number of the thermoelectric elements. The secondary by-pass circuits provide by-pass paths to failed thermoelectric elements, thereby allowing the remaining elements to continue operating. Primary by-pass circuit (30) is also provided to provide a by-pass path to all of the thermoelectric elements as required.

Abstract: A method of reversible data compression is disclosed. The method is an improvement on the Lempel-Ziv data compression method that does not require a prefix for every noncompressed data unit in the encoded data stream. A code is inserted at the beginning of each string of consecutive noncompressed data bytes to indicate that the string is of noncompressed data and the number of bytes in the string. By eliminating the requirement for a separate prefix for each noncompressed data, a higher compression ratio is achieved over conventional Lempel-Ziv encoding methods.

Abstract: A quantization apparatus for quantizing and word length limiting digitized stereo input signals including a stereo dither signal generating unit for generating stereo dither signals synthesized from at least two distinct dither signals not correlated to each other at an arbitrary ratio, a first addition unit for adding one of the stereo dither signals to one of the digital stereo input signals, a second addition unit for adding the other of the stereo dither signals to the other of the digital stereo input signals, a first quantization unit for quantizing and word length limiting an output signal of the first addition unit, and a second quantization unit for quantizing and word length limiting an output signal of the second addition unit. With the present quantization device, the stereo input signals may be quantized while cross-correlation between the left and right channel stereo input signals is maintained.

Abstract: Decoding and encoding of variable length data words and data strings is accelerated by testing for and processing more than one word or string per encoding or decoding cycle. In an encoding scheme wherein fixed length data words are encoded into variable length data strings, decoding is carried out by first receiving a data stream having a plurality of encoded data strings contained therein, and then testing at least a portion of the data stream to determine whether the portion contains one of a number of selected sets of multiple data strings. If the portion of the data stream contains one of the selected sets of multiple data strings, the multiple data strings are decoded into a corresponding set of multiple data words. This decoding procedure allows a plurality of encoded data strings to be decoded in a single decoding cycle. The procedure may be implemented using either a single lookup table or a set of split-level lookup tables.

Abstract: A metal oxide varistor in series with a semiconductor switch forms a protection circuit that reduces the steady-state voltage across the metal oxide varistor during normal operation, During an overvoltage transient condition, the semiconductor switch is gated on and the metal oxide varistor is placed in the voltage clamping mode.

Abstract: An ESD protection circuit includes a portion for protecting a pair of power lines and a portion for protecting an input/output pin. The power line protection portion includes at least three SCRs electrically connected in series between the power lines. A zener diode is electrically connected between a gate of the SCR at one end of the series and the negative power line, and a resistor is electrically connected between the gate of the one SCR and the positive power line. The gates of the other SCRs in the series are electrically connected to the negative power line or to their own cathode. The I/O pin protection portion includes a plurality of SCRs connected in series between the power lines with the I/O pin being connected between the SCR at one end of the series and the next adjacent SCR in the series. A separate zener diode is electrically connected between the gate of the SCR at the one end of the series and the gate of the next adjacent SCR and the negative power line.

Abstract: A variable length decoding apparatus contains a variable length code table of variable length codes which are used to decode variable length coded data and which are grouped together based on bit patterns of the variable length codes. The apparatus also includes a memory for storing the coded data in increments of N-bit data and for outputting a current N-bit data based on control signals generated in accordance with the contents of a previous N-bit data output from the memory. The apparatus also includes a controller which inputs the current N-bit data and compares the N-bit data with code state values that respectively identify the groups of the variable length codes. As a result, the controller determines the group of codes to which the current N-bit data belongs and outputs control signals based on such determination.

Abstract: A circuit for preventing ionization of air between contact points of a DC breaker switch when the breaker switch is opened includes a capacitor connected through a diode to form a shunt between the contact points when the switch is breaker switch is opened. A second switch is operated following shunting of residual voltage on the contact points so as to discharge the capacitor.

Abstract: A analog calibration signal including at least one frequency component is generated by a very pure signal source, such as a digital oscillator and a digital-to-analog converter (DAC) that has been calibrated to be ultralinear. The analog calibration signal is converted by an analog-to-digital converter (ADC) to a digital signal. The digital signal is digitally compensated in accordance with compensation coefficients to produce a compensated digital signal. The compensated digital signal is digitally processed to isolate and measure distortion components, and the compensation coefficients are adjusted in response to the distortion components in order to reduce the distortion components. Feedback causes the distortion components to be minimized so that the compensation coefficients correct the nonlinearity in the analog-to-digital converter.

Abstract: An over-voltage protection plug for telecommunication installations, including a housing with a printed-circuit board, a voltagesurge suppressor, a slider, a spring, an earth plate, a signalling element. Reliable protection against voltage surges is provided, wherein the solder position is loaded to a minimum extent only. The plug is composed of few parts only and further permits automated manufacture at low cost, and which clearly shows the tripped condition at the outside. The slider is pre-loaded over a support face and over an edge at the inner housing wall in the housing by the spring. A shaped part of solder material is loaded to a minimum extent only by the spring force (pressure force) of the slider.

Abstract: A superconducting fault current limiter composed of an induction coil wound around a core made of a soft magnetic material such as soft iron, ferrite or the like, a cylindrical superconductive body arranged in surrounding relationship with the induction coil and a cooling container formed to contain only the superconductive body therein and filled with cooling liquid such as liquid nitrogen or helium to immerse therein the superconductive body.

Abstract: A secondary battery protection unit comprises a discharge switch (41) and a charge switch (42) inserted in an electric path between a positive terminal (B1) and a negative terminal (B2) together with secondary cells (1 and 2) connected in cascade to the discharge and the charge switches (41 and 42), overcharge detection circuits (45 and 46), and an activation control circuit (17) including a current mirror circuit. The activation control circuit (17) detects a voltage difference between both ends of a combination or one of the discharge and the charge switches (41 and 42) to judge whether or not the secondary cells perform a charging operation or a discharging operation. Only during the charging operation, the activation control circuit (17) makes the current mirror circuit supply a bias voltage to the overcharge detection circuits (45 and 46) to allow activation thereof. During the discharging operation, supply of the bias voltage is inhibited to save excessive power consumption.