Abstract: A micro-electrochemical sensor contains magnetic compounds inserted within a substrate that exert a magnetic force of attraction on paramagnetic beads held in contact with an electrode. The magnetic compounds can be contained within a fluid that is introduced into a void in the substrate. The electrode can be spaced apart from the magnetic compounds by a dielectric multi-layer membrane. During the fabrication process, different layers within the membrane-electrode structure can be tuned to have compressive or tensile stress so as to maintain structural integrity of the membrane, which is thin compared with the size of the void beneath it. During a process of forming the structure of the sensor, the tensile stress in a TiW adhesion layer can be adjusted to offset a composite net compressive stress associated with the dielectric layers of the membrane. The membrane can also be used in forming both the electrode and the void.

Abstract: A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate.

Abstract: Provided are a semiconductor package and a manufacturing method thereof. A semiconductor package according to an embodiment comprises a chip part on a board, a mold member, and a plated layer on the mold member. The plated layer comprises an electrode pattern connected to a pattern of the board. The electrode pattern of the plated layer can be mounted at least one of at least one a chip part and at least one another semiconductor package.

Abstract: A loudspeaker system has a front loudspeaker enclosure (30) having at least one first loudspeaker (20) and a rear loudspeaker enclosure (50) having at least one second loudspeaker (60). The rear loudspeaker enclosure (50) is in the form of a bandpass enclosure.

Abstract: A circuit board structure, a packaging structure and a method for making the same are disclosed. First, a first substrate and a second substrate are provided. The first substrate includes a release film attached to a carrier. The second substrate includes a copper film covered with a solder mask. Second, the solder masked is patterned. Next, the release film and the patterned solder mask are pressed together so that the first substrate is attached to the second substrate. Then, the copper film is patterned to form a first pattern and a second pattern. The first pattern is in direct contact with the release film and the second pattern is in direct contact with the patterned solder mask. Later, a passivation is formed to cover the first pattern and the second pattern to form a circuit board structure. Afterwards, a package is formed on the carrier to form a packaging structure.

Abstract: A semiconductor device includes a first semiconductor chip including a first surface, a second surface and a first terminal arranged on the first surface, a second semiconductor chip including a first surface, a second surface and a second terminal arranged on the first surface of the second semiconductor chip, a support substrate including a first surface bonded to the second surfaces of the first semiconductor chip and the second semiconductor chip, and an isolation groove formed on the first surface of the support substrate. The isolation includes a pair of side surfaces continuously extending from opposing side surfaces of the first semiconductor chip and the second semiconductor chip, respectively, and the isolation groove is formed into the support substrate to extend from the first surface of the support substrate. The isolation groove has a depth less than a thickness of the support substrate.

Abstract: A semiconductor device, in which an integrated circuit portion and an antenna are easily connected, can surely transmit and receive a signal to and from a communication device. The integrated circuit portion is formed of a thin film transistor over a surface of a substrate so that the area occupied by the integrated circuit portion is increased. The antenna is provided over the integrated circuit portion, and the thin film transistor and the antenna are connected. Further, the area over the substrate occupied by the integrated circuit portion is 0.5 to 1 times as large as the area of the surface of the substrate. Thus, the size of the integrated circuit portion can be close to the desired size of the antenna, so that the integrated circuit portion and the antenna are easily connected and the semiconductor device can surely transmit and receive a signal to and from the communication device.

Abstract: A power semiconductor diode is provided. The power semiconductor diode includes a semiconductor substrate having a first emitter region of a first conductivity type, a second emitter region of a second conductivity type, and a drift region of the first conductivity type arranged between the first emitter region and the second emitter region. The drift region forms a pn-junction with the second emitter region. A first emitter metallization is in contact with the first emitter region. The first emitter region includes a first doping region of the first conductivity type and a second doping region of the first conductivity type. The first doping region forms an ohmic contact with the first emitter metallization, and the second doping region forms a non-ohmic contact with the first emitter metallization. A second emitter metallization is in contact with the second emitter region.

Abstract: A foldable thin film transistor (TFT) is provided, the foldable TFT including: a foldable substrate; source and drain electrodes interconnected on the foldable substrate; a channel layer including nanofibers of an organic semiconductor connecting the source and drain electrodes; a gate electrode electronically connected with the source and drain electrodes and the channel layer; and a gate insulating layer disposed between the channel layer and the gate electrode and comprising an ionic liquid and a resin.

Abstract: A semiconductor device including a cell region and a peripheral region, the semiconductor device comprising: a guard ring region provided between the cell region and the peripheral region, the guard ring region having a barrier structure.

Abstract: An electronic subassembly and associated method for the production of an electronic subassembly include a semiconductor layer bearing at least a first transistor having an adjustable threshold voltage is joined to an insulator layer and in which a first trapping zone is formed at a predetermined first depth. The first trapping zone extends at least beneath a channel of the first transistor and includes traps of greater density than the density of traps outside the first trapping zone, in such a way that the semiconductor layer and the first trapping zone are capacitively coupled. The useful information from the first transistor includes the charge transport within this transistor. A second trapping zone can be formed that extends at least beneath a channel of a second transistor that is formed by a second implantation with an energy and/or a dose and/or atoms that differ from those used to form the first trapping zone.

Abstract: An IC chip includes a matrix of solder bumps aligned in lines of a first axis and lines of a second axis. Adjacent solder bumps aligned in the first axis have a minimum distance and adjacent solder bumps aligned in the second axis have the minimum distance. The matrix includes a first pair of solder bumps aligned in a first line of the first axis and configured to transmit a first pair of differential signals, and a second pair of solder bumps aligned in a second line of the first axis next to the first line and configured to transmit a second pair of differential signals. The second pair of solder bumps are staggered from the first pair of the solder bumps to avoid in alignment with the first pair of solder bumps in the second axis.

Abstract: Disclosed is a substrate for a semiconductor package in which leakage of radiation noise from a gap between a semiconductor element and a mounting substrate can be prevented. The substrate for the semiconductor package includes a coplanar waveguide including a signal and ground electrodes on the mounting substrate, the signal electrode flip-chip connected to the semiconductor element, the ground electrodes arranged on both sides of the signal electrode with intervals therebetween. A step part is formed in the ground electrodes in an outer circumferential part of a mounting region of the semiconductor element, the step part having a larger distance between upper surfaces of the mounting substrate and the ground electrode in the outer circumferential part of the mounting region than such distance in the mounting region, and an insulator for covering the signal electrode in the outer circumferential part of the mounting region is formed.

Abstract: An electronic device can include a nonvolatile memory cell, wherein the nonvolatile memory cell can include an access transistor, a read transistor, and an antifuse component coupled to the access transistor and the read transistor. In an embodiment, the read transistor can include a gate electrode, and the antifuse component can include a first electrode and a second electrode overlying the first electrode. The gate electrode and the first electrode can be parts of the same gate member. In another embodiment, the access transistor can include a gate electrode, and the antifuse component can include a first electrode, an antifuse dielectric layer, and a second electrode. The electronic device can further include a conductive member overlying the antifuse dielectric layer and the gate electrode of the access transistor, wherein the conductive member is configured to electrically float. Processes for making the same are also disclosed.

Abstract: A method for producing semiconductor components on a substrate including photolithographic patterning steps, in which method, on the substrate, a first layer to be patterned is applied and a second layer serving as a mask layer for the first layer to be patterned is applied, wherein a third layer serving as a mask for the second layer is applied, and wherein at least two photolithographic patterning processes are carried out successively for the second layer, wherein, during one of the patterning processes, after the production of a structure made from a photosensitive layer for the provision of a mask layer for a patterning process at the third layer, positive ramp angles ? are produced at the patterning edges of the third layer, as a result of which the structures remaining free, given a thickness h of the third layer, decrease in size by a value D=2*h/tan ?.

Abstract: An electromigration and stress migration enhancement liner is provided for use in an interconnect structure. The liner includes a metal that has a thickness at a bottom of the at least one via opening and on an exposed portion of an underlying conductive feature that is greater than a remaining thickness that is located on exposed sidewalls of the interconnect dielectric material. The thinner portion of the electromigration and stress migration enhancement liner is located between the interconnect dielectric material and an overlying diffusion barrier. The thicker portion of the electromigration and stress migration enhancement liner is located between the underlying conductive feature and the diffusion barrier as well as between an adjacent dielectric capping layer and the diffusion barrier. The remainder of the at least one via opening is filled with an adhesion layer and a conductive material.

Abstract: In an organic light-emitting display device and a method of manufacturing the same, the display device may include: a thin-film transistor including an active layer, a gate electrode including a first electrode which includes nano-Ag on an insulating layer formed on the active layer and a second electrode on the first electrode, a source electrode, and a drain electrode; an organic light-emitting device including a pixel electrode electrically connected to the thin-film transistor and formed of the same layer as, and using the same material used to form, the first electrode, an intermediate layer including an emissive layer, and an opposite electrode covering the intermediate layer and facing the pixel electrode; and a pad electrode formed of the same layer as, and using the same material used to form, the first electrode in a pad area located outside of a light-emitting area.

Abstract: An apparatus that comprises a power ground/arrangement that comprises a first semiconductor die configured as a central processing unit (CPU). The power/ground arrangement further comprises a first metal layer that provides only one of (i) a power signal and (ii) a ground signal, and a second metal layer that provides the other one of (i) the power signal and (ii) the ground signal. The apparatus further comprises a second semiconductor die configured as a memory that is coupled to the power/ground arrangement. The second semiconductor die is configured to receive power signals and ground signals from the power/ground arrangement. The second semiconductor die is further configured to provide signals to the CPU via the power/ground arrangement and to receive signals from the CPU via the power/ground arrangement. The second semiconductor die is coupled to the power/ground arrangement only along a single side of the second semiconductor die.

Abstract: The description relates to a bonding pad for a semiconductor device deposited. The first region comprising aluminum deposited at a high temperature having a large grain size. The second region comprising aluminum deposited at a lower temperature having a smaller grain size.

Abstract: Disclosed is a flexible radiation detector including a substrate, a switching device on the substrate, an energy conversion layer on the switching device, a top electrode layer on the energy conversion layer, a first phosphor layer on the top electrode layer, and a second phosphor layer under the substrate.