Abstract: In one general aspect, a termination structure can include a plurality of pillars of a first conductivity type formed inside a termination region of a second conductivity type opposite the first conductivity type where the plurality of pillars define a plurality of concentric rings surrounding an active area of a semiconductor device. The termination structure can include a conductive field plate where the plurality of pillars includes a first pillar coupled to the conductive field plate. The termination structure can include a dielectric layer where the plurality of pillars include a second pillar insulated by the dielectric layer from a portion of the conductive field plate disposed directly above the second pillar included in the plurality of pillars.

Abstract: In an ultra high voltage lateral GaN structure having a 2DEG region extending between two terminals, an isolation region is provided between the two terminals to provide for reversible snapback.

Abstract: A pad for a line which supplies an electric power potential is disposed on a semiconductor integrated circuit and a pad which is not electrically connected to any other electric circuit is disposed on a semiconductor integrated circuit board, and the two pads are connected through a bonding wire. An LC resonant circuit is configured with ease using a floating capacitance C of the pad which is in an electrically open state and which is disposed in a vacant region and an inductance value L of the bonding wire which is disposed in a three-dimensional manner. High-frequency noise is filtered and high-density implementation is realized.

Abstract: Disclosed is an integrated circuit (IC) comprising a substrate (10) including a plurality of circuit elements and a metallization stack (20) covering said substrate for providing interconnections between the circuit elements, wherein the top metallization layer of said stack carries a plurality of metal portions (30) embedded in an exposed porous material (40) for retaining a liquid, said porous material laterally separating said plurality of metal portions. An electronic device comprising such an IC and a method of manufacturing such an IC are also disclosed.

Abstract: A method of fabricating a semiconductor device includes forming a first set of gate electrodes over a substrate, adjacent gate electrodes of the first set of gate electrodes being separated by a first gap width, and having a first gate width. The method includes forming a second set of gate electrodes over the substrate, adjacent gate electrodes of the second set of gate electrodes being separated by a second gap width less than the first gap width, and having a second gate width greater than the first gate width. The method further includes forming a first set of spacer structures on sidewalls of the first and second sets of gate electrodes. The method further includes forming a second set of spacer structures abutting the first set of spacer structures and removing a subset of the second set of spacer structures over the sidewalls of the second set of gate electrodes.

Abstract: A contact to a semiconductor including sequential layers of Cr, Ti, and Al is provided, which can result in a contact with one or more advantages over Ti/Al-based and Cr/Al-based contacts. For example, the contact can: reduce a contact resistance; provide an improved surface morphology; provide a better contact linearity; and/or require a lower annealing temperature, as compared to the prior art Ti/Al-based contacts.

Abstract: The present invention relates to a multi-luminous element and a method for manufacturing the same. The present invention provides the multi-luminous element comprising: a buffer layer disposed on a substrate; a first type semiconductor layer disposed on the buffer layer; a first active layer which is disposed on the first type semiconductor layer and is patterned to expose a part of the first type semiconductor layer; a second active layer disposed on the first type semiconductor layer which is exposed by the first active layer; and a second type semiconductor layer disposed on the first active layer and the second active layer, the first and second active layers being repeatedly disposed in the horizontal direction, and the method for manufacturing the same.

Abstract: A method for making the same is disclosed. First, a first substrate and a second substrate are provided. The first substrate includes a release film attached to a carrier. The second substrate includes a copper film covered with a solder mask. Second, the solder masked is patterned. Next, the release film and the patterned solder mask are pressed together so that the first substrate is attached to the second substrate. Then, the copper film is patterned to form a first pattern and a second pattern. The first pattern is in direct contact with the release film and the second pattern is in direct contact with the patterned solder mask. Later, a passivation is formed to cover the first pattern and the second pattern to form a circuit board structure. Afterwards, a package is formed on the carrier to form a packaging structure.

Abstract: Forming of filled isolation trenches, in particular the transition area in trenches and recesses free of silicon during the realization of MEMS structures of SOI wafers. A reliable dielectric insulation of adjacent silicon regions is to be obtained. The insulation is achieved by filled isolation trenches. The end portions of the trench fill that are freed from the surrounding silicon by etching are free of conductive not completely removed silicon strips in the recess including the active sensor structure. This is accomplished by slanted wall of isolation trenches. Additionally, the trench fill should be removable at the transition area in an efficient manner. The technological realization does not require specific additional process steps.

Abstract: A circuit board structure at least includes a patterned solder mask, a first conductive pattern, a second conductive pattern adjacent to the first conductive pattern and in direct contact with the patterned solder mask and a passivation respectively covering the first conductive pattern and the second conductive pattern.

Abstract: The invention relates to an ultrathin semiconductor circuit having contact bumps and to a corresponding production method. The semiconductor circuit includes a bump supporting layer having a supporting layer thickness and having a supporting layer opening for uncovering a contact layer element being formed on the surface of a semiconductor circuit. An electrode layer is situated on the surface of the contact layer element within the opening of the bump supporting layer, on which electrode layer is formed a bump metallization for realizing the contact bump. On account of the bump supporting layer, a thickness of the semiconductor circuit can be thinned to well below 300 micrometers, with the wafer reliably being prevented from breaking. Furthermore, the moisture barrier properties of the semiconductor circuit are thereby improved.

Abstract: In various embodiments, an assembly having a microstructure is provided, the device includes a cylindrical capture receptacle associated with a substrate, the capture receptacle comprising of a material having an expansion coefficient and comprising alignment structures having alignment projections extending inward from a periphery of the cylindrical capture receptacle. In one embodiment, the projections include a large width alignment projection and plurality of small width alignment projections. A plurality of medium width alignment projections also may be provided. A cylindrical key is associated with the microstructure and has a smaller circumference than the cylindrical capture receptacle and is comprised of a material having an expansion coefficient greater than the expansion coefficient of the cylindrical capture receptacle. The cylindrical key includes alignment receptacles spaced about a periphery of the cylindrical base to receive corresponding alignment projections.

Abstract: A memory circuit arrangement and a fabrication method are disclosed. The memory circuit arrangement has a memory cell area. The memory cell area contains memory cell transistors, one column of which are selected using a triple gate area selection transistor. The transistor has gate area that extends into isolating trenches. The isolating trenches isolate the memory cell in different columns of the memory cell array.

Abstract: A semiconductor substrate is provided having a first metal layer formed over a first insulating layer. A second insulating layer is formed having a first damascene opening, the first opening having a second insulating layer portion formed therein. A resist layer is deposited to fill the first opening and the resist layer is thereafter patterned to form an etching mask for etching a second damascene opening. The second opening is etched into a portion of the second insulating layer, the second opening exposing a portion of the first metal layer. A second metal layer is formed to include filling the first and second damascene openings embedding the second insulating layer portion in the second metal layer. The second metal layer is planarized and a passivation layer is formed above the second insulating layer and the second metal layer, wherein the passivation layer partially covers the second metal layer.

Abstract: A non-volatile semiconductor memory device and a method of manufacturing the same of the embodiments are provided. The non-volatile semiconductor memory device includes: drain contact plugs formed in memory cell regions and having bottom ends joined to drain diffusion layers of the respective memory cells; a local interconnect provided to extend in a WL direction across the memory cell regions and a shunt region, and having a bottom end joined commonly to plural source diffusion layers; drain via plugs formed in the memory cell regions and having bottom ends joined to the top ends of the respective drain contact plugs; and a power supply via for source formed in the shunt region to extend in a BL direction, and having a bottom end joined to the top end of the local interconnect.

Abstract: Dual shadow mask design can overcome the size and resolution limitations of shadow masks to provide capacitor structures with small effective areas. The capacitor structures have bottom and top electrode layers patterned using shadow masks, sandwiching a dielectric layer. The effective areas of the capacitors are the overlapping areas of the top and bottom electrodes, thus allowing small area sizes without subjected to the size limitation of the electrodes. The dual shadow mask design can be used in conjunction with high productivity combinatorial processes for screening and optimizing dielectric materials and fabrication processes.

Abstract: An ohmic electrode for a p-type SiC semiconductor, and a method of forming the ohmic electrode. The ohmic electrode has an ohmic electrode layer, which has an amorphous structure and which is made of a Ti(1-x-y)Si(x)C(y) ternary film of which a composition ratio is within a composition range that is surrounded by two lines and two curves expressed by an expression x=0 (0.35?y?0.5), an expression y=?1.120x+0.5200 (0.1667?x?0.375), an expression y=1.778(x?0.375)2+0.1 (0?x?0.375) and an expression y=?2.504x2?0.5828x+0.5 (0?x?0.1667) and that excludes the line expressed by the expression x=0. The ohmic layer is directly laminated on a surface of a p-type SiC semiconductor.

Abstract: An LDMOS device includes a gate which is formed on and/over over a substrate; a source and a drain which are arranged to be separated from each other on both sides of the substrate with the gate interposed therebetween; and a field oxide film formed to have a step between the gate and the drain. The LDMOS device further includes a drift region formed of first conduction type impurity ions between the gate and the drain in the substrate; and at least one internal field ring formed in the drift region by selectively implanting a second conduction type impurity in accordance with the step of the field oxide film.

Abstract: An organic EL display device (1) includes an element substrate (30), a sealing substrate (20) facing the element substrate (30), an organic EL element (4) provided on the element substrate (30) and between the element substrate (30) and the sealing substrate (20), a first sealing member (5) made of fritted glass and provided between the element substrate (30) and the sealing substrate (20), and configured to weld the element substrate (30) and the sealing substrate (20) to seal the organic EL element (4), a resin member (14) provided between the sealing substrate (20) and the organic EL element (4) and configured to cover a surface of the organic EL element (4), and a second sealing member (16) formed of a resin and provided between the element substrate (30) and the sealing substrate (20).

Abstract: According to one embodiment, a semiconductor device includes first to n-th semiconductor layers (n is a natural number equal to or more than 2) being stacked in order from a surface of an insulating layer in a first direction perpendicular to the surface of the insulating layer, the first to n-th semiconductor layers extending in a second direction parallel to the surface of the insulating layer, the first to n-th semiconductor layers being insulated from each other, a common electrode connected to the first to n-th semiconductor layers in a first end of the second direction thereof, and a layer select transistor which uses the first to n-th semiconductor layers as channels and which selects one of the first to n-th semiconductor layers.