Abstract: In a light-source device (10) of this invention, integrated light emission intensity from 460 nm to 500 nm is higher than integrated light emission intensity from 415 nm to 460 nm in an emission spectrum of white light. This allows provision of a light-source device which emits white light easy on a human eye.

Abstract: To provide a semiconductor device having a structure capable of forming a superjunction with less thermal history, a semiconductor device is provided, the semiconductor device including a contact trench formed between two gate trenches, penetrating through a source region, and including its lower end arranged in a base region, and a second conductivity-type protruding portion formed protruding toward a lower side from the lower end of the base region in a region opposite to the lower end of the contact trench, wherein the depth from the upper end of the source region to a lower end of the protruding portion is 3 ?m or more, and a carrier concentration Nd in a first conductivity-type region adjacent to the protruding portion in a lateral direction perpendicular to a depth direction and a carrier concentration Na of the protruding portion satisfy a predetermined equation.

Abstract: An integrated circuit product includes an NFET FinFET device having a first fin that is made entirely of a first semiconductor material and a PFET FinFET device that includes a second fin having an upper portion and a lower portion, wherein the lower portion is made of the first semiconductor material and the upper portion is made of a second semiconductor material that is different from the first semiconductor material. A silicon nitride liner is positioned on and in contact with the lower portion of the second fin, wherein the silicon nitride liner is not present on or adjacent to the upper portion of the second fin or on or adjacent to any portion of the first fin.

Abstract: A semiconductor device or a memory device with low power consumption and a small area is provided. The semiconductor device includes a sense amplifier and a memory cell. The memory cell is provided over the sense amplifier. The sense amplifier includes a first transistor and a second transistor. The memory cell includes a third transistor and a capacitor. The first transistor is a p-channel transistor. The second transistor and the third transistor each include an oxide semiconductor in a channel formation region. The third transistor is preferably provided over the capacitor.

Abstract: A semiconductor device includes a wiring substrate, a semiconductor element mounted on the wiring substrate, a heat dissipation plate bonded to an upper surface of the semiconductor element with an adhesive, and an encapsulation resin that fills a gap between the heat dissipation plate and the wiring substrate. The heat dissipation plate includes a body overlapped with the semiconductor element in a plan view. The body is larger than the semiconductor element in a plan view. A projection is formed integrally with the body. The projection projects outward from an end of the body and is located at a lower position than the body. The encapsulation resin covers upper, lower, and side surfaces of the projection. The body includes an upper surface exposed from the encapsulation resin.

Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate including an active cell areas and a termination area. The semiconductor power device further comprises a plurality of gate trenches formed at a top portion of the semiconductor substrate in the active cell area wherein each of the gate trenches is partially filled with a conductive gate material with a top portion of the trenches filled by a high density plasma (HDP) insulation layer. The semiconductor power device further comprises mesa areas of the semiconductor substrate disposed between the gate trenches wherein the mesa areas are recessed and having a top mesa surface disposed vertically below a top surface of the HDP insulation layer wherein the HDP insulation layer covering over the conductive gate material constituting a stick-out boundary-defining layer surrounding the recessed mesa areas in the active cell areas between the gate trenches.

Abstract: A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.

Abstract: An electrical device that includes at least one n-type field effect transistor including a channel region in a type III-V semiconductor device, and at least one p-type field effect transistor including a channel region in a germanium containing semiconductor material. Each of the n-type and p-type semiconductor devices may include gate structures composed of material layers including work function adjusting materials selections, such as metal and doped dielectric layers. The field effect transistors may be composed of fin type field effect transistors. The field effect transistors may be formed using gate first processing or gate last processing.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a material layer over a semiconductor substrate and forming a hard mask layer over the material layer. The hard mask layer contains metal. The method also includes forming an opening in the hard mask layer using a plasma etching process, and a gas mixture used in the plasma etching process includes a nitrogen-containing gas, a halogen-containing gas, and a carbon-containing gas. The method further includes etching the material layer through the opening in the hard mask layer to form a feature opening in the material layer.

Abstract: Reduction of power consumption of a semiconductor device is aimed. The semiconductor device includes a cell region where a vertical power MOSFET is formed and an intermediate region surrounding the cell region. In each of the cell region and the intermediate region, a plurality of p-type column regions and a plurality of n-type column regions are alternately formed. The n-type column region arranged in the cell region has a defect region formed therein, whereas the n-type column region arranged in the intermediate region does not have the defect region. A defect density in the n-type column region arranged in the cell region is larger than that in the n-type column region arranged in the intermediate region.

Abstract: A semiconductor device and a manufacturing method for the same are provided in such a manner that the oxygen barrier film and the conductive plug in the base of a capacitor are prevented from being abnormally oxidized. A capacitor is formed by layering a lower electrode, a dielectric film including a ferroelectric substance or a high dielectric substance, and an upper electrode in this order on top of an interlayer insulation film with at least a conductive oxygen barrier film in between, and at least a portion of a side of the conductive oxygen barrier film is covered with an oxygen entering portion or an insulating oxygen barrier film.

Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a semiconductor fin; a gate dielectric positioned above a first region of the semiconductor fin; a spacer positioned above a second region of the semiconductor fin and adjacent to the gate dielectric; and a source/drain region contacting a third region of the semiconductor fin; wherein the first region of the semiconductor fin includes substantially vertical sidewalls, and the third region of the semiconductor fin includes sloped sidewalls.

Abstract: According to the present invention, a light-emitting diode with improved light extraction efficiency comprises: a semiconductor laminated structure including an N-layer, a light-emitting layer, and a P-layer formed on a substrate; an N-type electrode formed on the N-layer; and a P-type electrode formed on the P-layer, wherein the N-type electrode and the P-type electrode include a pad electrode and a dispersion electrode, and the N-type electrode and/or the P-type electrode includes a reflective electrode layer for reflecting light onto the dispersion electrode. Thus, the light-emitting diode has a reflective electrode layer on the electrode so as to improve light extraction efficiency. Further, a reflective layer is patterned beneath a pad unit, thus forming roughness and improving adhesion.

Abstract: An optoelectronic device for detecting radiation, comprising a semiconductor body including: a cathode region delimited by a front surface, having a first conductivity type and including a bottom layer; an anode region having a second conductivity type, which extends in the cathode region starting from the front surface and forms a surface junction with the cathode region; and a buried region having the second conductivity type, which extends within the cathode region and forms a buried junction with the bottom layer. The cathode region further includes a buffer layer, which is arranged underneath the anode region and overlies, in direct contact, the bottom layer. The buffer layer has a doping level higher than the doping level of the bottom layer.

Abstract: A light-emitting arrangement includes a radiation-emitting semiconductor chip that, during operation, emits primary radiation at least from a main emission surface, a first conversion element that absorbs part of the primary radiation and emits secondary radiation, and a deflection element that causes a direction change for part of the primary radiation, wherein the first conversion element is arranged in a lateral direction next to the radiation-emitting semiconductor chip, the deflection element guides part of the primary radiation onto the first conversion element, and the light-emitting arrangement, in operation, emits mixed light including the primary radiation and the secondary radiation.

Abstract: A method includes providing a semiconductor structure comprising multiple fins and a gate structure on the fins. The method also includes removing a portion of the fins not covered by the gate structure to form a remaining portion of the fins, performing a first epitaxially growth process to form first epitaxially grown regions on the remaining portion of the fins, performing a first annealing process so that an upper portion of the first epitaxially grown regions is greater than a lower portion, performing a second epitaxially growth process on the annealed first epitaxially grown regions to form second epitaxially grown regions, and performing a second annealing process on the second epitaxially grown regions, so that an upper portion of the second epitaxially grown regions is greater than a lower portion. The second epitaxially grown regions are separated from each other before and after the second annealing process.

Abstract: A multichip module (MCM) device include a first die including functional circuitry bonded by a plurality of inter-die bond wires (bond wires) to a second die having functional circuitry. A first channel (Channel A) and second channel (Channel B) each have separate top and bottom signal paths (signal paths) including one of the bond wires. A failure of any of the signal paths does not affect functionality of the device. The first die includes input pins including a first input pin (P1), a second input pin (P2), and coupling circuitry including cross-channel test circuitry positioned between the input pins and the functional circuitry. The coupling circuitry provides for Channel A and Channel B a first configuration for normal mode operation and a second configuration for test mode operation for single bond wire testing for checking continuity of any of the bond wires.

Abstract: A semiconductor memory device according to one embodiment, includes an interconnect extending in a first direction, a semiconductor member extending in a second direction crossing the first direction, an electrode provided between the interconnect and the semiconductor member, a first insulating film provided between the interconnect and the electrode, a second insulating film provided between the first insulating film and the electrode, a third insulating film provided between the electrode and the semiconductor member, and a metal-containing layer provided between the first insulating film and the second insulating film or inside the first insulating film, and having a metal surface concentration of 1×1014 cm?2 or more and 5×1015 cm?2 or less.

Abstract: An electronics package includes an insulating substrate, a first electrical component coupled to a first surface of the insulating substrate, and a first conductor layer formed on the first surface of the insulating substrate. A second conductor layer is formed on a second surface of the insulating substrate, opposite the first surface, the second conductor layer extending through vias in the insulating substrate to contact at least one contact pad of the first electrical component and couple with the first conductor layer. The electronics package also includes a second electrical component having at least one contact pad coupled to the first conductor layer. The first conductor layer has a thickness greater than a thickness of the second conductor layer.