Abstract: An electronics package includes an insulating substrate and electrical components coupled to a first surface of the insulating substrate. A multi-thickness conductor layer is formed on a second surface of the insulating substrate opposite the first surface. The multi-thickness conductor layer extends through vias in the insulating substrate to connect with contact pads of the electrical components. The multi-thickness conductor layer has a first thickness in a region proximate the first electrical component and a second thickness in a region proximate the second electrical component, the first thickness greater than the second thickness. The electronics package also includes a first redistribution layer having a conductor layer formed atop a portion of the multi-thickness conductor layer having the second thickness. A top surface of the conductor layer is co-planar with or substantially co-planar with a top surface of a portion of the multi-thickness conductor layer having the first thickness.

Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a first conductive film provided on a first region of the first insulating film, a second conductive film provided on a second region of the first insulating film, a first stacked body provided on the first conductive film, a second stacked body provided on the second conductive film, a first semiconductor pillar, and two conductive pillars. In the first stacked body, a second insulating film and an electrode film are stacked alternately. In the second stacked body, a third insulating film and a first film are stacked alternately. The two conductive pillars extend in the first direction through the second stacked body, are separated from the second conductive film, sandwich the second conductive film, and are connected at a bottom ends of the second conductive pillars to the semiconductor substrate.

Abstract: A substrate includes a base made of a metal material, a thermally conductive, light-reflective ceramic insulating layer, and a buffer layer formed between the base and the ceramic insulating layer and having a smaller linear expansion coefficient than the base.

Abstract: An array substrate and a manufacturing method thereof, a display panel and a display device are disclosed. The method for manufacturing an array substrate includes: forming a first via hole for connecting a second transparent electrically conductive layer and a gate line layer, a second via hole for connecting a first transparent electrically conductive layer and the second transparent electrically conductive layer, and a third via hole for connecting the second transparent electrically conductive layer and a source/drain electrode layer on a base substrate through patterning process; performing a filling process on the first via hole, the second via hole and the third via hole during a pattern of second transparent electrically conductive layer is being formed, such that each of the three via holes has a top surface which is flush with the second transparent electrically conductive layer surrounding the respective via holes.

Abstract: Provided is a highly integrated semiconductor device, a semiconductor device with large storage capacity with respect to an area occupied by a capacitor, a semiconductor device capable of high-speed writing, a semiconductor device capable of high-speed reading, a semiconductor device with low power consumption, or a highly reliable semiconductor device. The semiconductor device includes a first transistor, a second transistor, and a capacitor. A conductor penetrates and connects the first transistor, the capacitor, and the second transistor. An insulator is provided on a side surface of the conductor that penetrates the capacitor.

Abstract: A semiconductor memory device includes a plurality of first electrode layers stacked in a first direction; a semiconductor layer extending in the first direction in the plurality of first electrode layers; a first insulating layer extending in the first direction along the semiconductor layer between the semiconductor layer and each of the plurality of first electrode layers; a second insulating layer covering the periphery of the plurality of first electrode layers; a resistive body provided on the second insulating layer; and a third insulating layer provided between the resistive body and the second insulating layer, the third insulating layer including the same material as the material of the first insulating layer.

Abstract: An N-type MOSFET and a method for manufacturing the same are disclosed. In one aspect, the method comprises forming source/drain regions in a semiconductor substrate. The method also includes forming an interfacial oxide layer on the semiconductor substrate. The method also includes forming a high-k gate dielectric layer on the interfacial oxide layer. The method also includes forming a first metal gate layer on the high-k gate dielectric layer. The method also includes implanting dopants into the first metal gate layer through conformal doping. The method also includes annealing a gate stack to change an effective work function of the gate stack which includes the first metal gate layer, the high-k gate dielectric, and the interfacial oxide layer.

Abstract: A resistive random access memory overcomes the low reliability of the conventional resistive random access memory. The resistive random access memory includes a resistance changing layer and two electrode layers. The two electrode layers are coupled with the resistance changing layer. Each of the two electrode layers includes a doping area containing a heavy element. In such an arrangement, the above deficiency can be overcome.

Abstract: The present disclosure involves a method of fabricating a semiconductor device in a semiconductor technology node that is 5-nanometer or smaller. An opening is formed that extends through a plurality of layers over a substrate. A barrier layer is formed on surfaces of the opening. A liner layer is formed over the barrier layer in the opening. The barrier layer and the liner layer have different material compositions. The opening is filled with a non-copper metal material. The non-copper material is formed over the liner layer. In some embodiments, the non-copper metal material includes cobalt.

Abstract: An image pickup apparatus is configured with an image pickup device on which a plurality of bumps are arranged in line on an outer circumferential portion of a light receiving surface; and a flexible wiring board including a plurality of inner leads each of which is configured with a distal end portion, a bending portion and a rear end portion, the distal end portion being compression-bonded to a bump, and the rear end portion being arranged parallel to a side face of the image pickup device with the bending portion interposed between the distal end portion and the rear end portion. A height of a light receiving portion side of the bumps is lower than a height of a side face side; and each of the inner leads is plastically transformed according to a shape of a top face of the bumps.

Abstract: A method comprises forming material to be etched over a substrate. An etch mask comprising a silicon nitride-comprising region is formed elevationally over the material. The etch mask comprises an elevationally-extending mask opening in the silicon nitride-comprising region that has a minimum horizontal open dimension that is greater in an elevationally-innermost portion of the region than in an elevationally-outermost portion of the region. The elevationally-outermost portion has a greater etch rate in at least one of HF and H3PO4 than does the elevationally-innermost portion. The etch mask is used as a mask while etching an elevationally-extending mask opening into the material. The silicon nitride-comprising region is exposed to at least one of HF and H3PO4 to increase the minimum horizontal open dimension in the elevationally-outermost portion to a greater degree than increase, if any, in the minimum horizontal open dimension in the elevationally-innermost portion.

Abstract: A memory circuit includes a first active structure extending along a first direction, a second active structure extending along the first direction, a first conductive structure extending along a second direction, and a lowest via plug layer over the first conductive structure. The first active structure has a shared source portion corresponding to a source node of a first memory cell of the memory circuit and a source node of a second memory cell of the memory circuit. The second active structure has a shared source portion corresponding to a source node of a third memory cell of the memory circuit and a source node of a fourth memory cell of the memory circuit. The first conductive structure electrically connects the shared source portion of the first active structure with the shared source portion of the second active structure.

Abstract: The present disclosure provides an array substrate comprising a plurality of data lines and a plurality of groups of gate lines, a display panel comprising the array substrate, a display device comprising the display panel and an electronic device comprising the display device. The plurality of data lines and the plurality of groups of gate lines intersect each other for dividing the array substrate into a plurality of pixel units. Each group of gate lines defines a row of a plurality of pixel units and comprises a first gate line and a second gate line. Each pixel unit comprises a first pixel electrode and a second pixel electrode, the first pixel electrode corresponds to the second gate line and the second pixel electrode corresponds to the first gate line.

Abstract: An embodiment provides a light-emitting device package comprising: a first lead frame; a second lead frame; a light-emitting device electrically connected to the first lead frame and the second lead frame; a molding unit arranged to surround the light-emitting device; and an oxynitride-based phosphor represented by chemical formula LXMYOaNbAcBd:zR (1?X?3, 3?Y?7, 0.001?Z?1.0, 0?a?5, 0.1?b?9, 0.001?c?0.3, 0.001?d?0.3), and the light-emitting device package of the present embodiment can implement a white color light having excellent luminance and color rendering index.

Abstract: A multi-layer semiconductor device includes two or more semiconductor sections, each of the semiconductor sections including at least at least one device layer having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The electrical connections correspond to first conductive structures. The multi-layer semiconductor device also includes one or more second conductive structures which are provided as through oxide via (TOV) or through insulator via (TIV) structures. The multi-layer semiconductor device additionally includes one or more silicon layers. At least a first one of the silicon layers includes at least one third conductive structure which is provided as a through silicon via (TSV) structure. The multi-layer semiconductor device further includes one or more via joining layers including at least one fourth conductive structure. A corresponding method for fabricating a multi-layer semiconductor device is also provided.

Abstract: An array substrate and a display device, the array substrate comprises a fan-out area, an edge area and a display area for performing display, the fan-out area and the edge area are connected with the display area and located on two non-adjacent sides of the display area respectively; a plurality of wirings are arranged on the array substrate, and the wirings are routed through the display area and extend into the edge area, the input end of each wiring is located in the fan-out area; pads are configured for the wirings respectively are located on the side far away from the input end of each wiring, and the pads are located in the edge area.

Abstract: This semiconductor device includes: a semiconductor layer that is formed of first conductivity-type SiC; a plurality of trenches that are formed in the semiconductor layer; second conductivity-type column regions that are formed along the inner surfaces of the trenches; a first conductivity-type column region that is disposed between the adjacent second conductivity-type column regions; and insulating films that are embedded in the trenches. The semiconductor device is capable of improving a withstand voltage by means of a super junction structure. The semiconductor device may also include an electric field attenuation section for attenuating electric field intensity of a surface section of the first conductivity-type column region.

Abstract: A non-volatile memory device that limits the temperature excursion of a selector during operation to enhance the cycling life of the non-volatile memory device. A selector, in line with a memory element, may be degraded with repeated temperature excursions as current passes through a stack during the read/write process. The selector changes from an amorphous state to become crystalline thus reducing the life of a memory device. The memory device includes a word line, a bit line disposed perpendicular to the word line, a stack—including a memory element, a selector, and a spacer—disposed between the word line and bit line, and one or more insulating layers surrounding an outer surface of the stack disposed between the word line and bit line. By surrounding the selector with a high thermal conductive heat-sink material, heat is directed away from the selector helping maintain the selector's amorphous state longer.

Abstract: A nanowire comprises a source region, a drain region and a channel region. The source region is modified to reduce the lifetime of minority carriers within the source region. In an embodiment the modification may be performed by implanting either amorphizing dopants or lifetime reducing dopants. Alternatively, the source may be epitaxially grown with a different materials or process conditions to reduce the lifetime of minority carriers within the source region.

Abstract: A semiconductor device includes a gate structure on a substrate, a source/drain layer on a portion of the substrate adjacent the gate structure, a first contact plug contacting an upper surface of the source/drain layer, and a second contact plug contacting upper surfaces of the gate structure and the first contact plug. A bottom surface of the second contact plug has a first portion not contacting the upper surface of the first contact plug, and the first portion is higher than the upper surface of the gate structure.