Abstract: According to one aspect, a method for determining, for a memory allocation, placements in a memory area of data blocks generated by a neural network, comprises a development of an initial sequence of placements of blocks, each placement being selected from several possible placements, the initial sequence being defined as a candidate sequence, a development of at least one modified sequence of placements from a replacement of a given placement of the initial sequence by a memorized unselected placement, and, if the planned size of the memory area obtained by this modified sequence is less than that of the memory area of the candidate sequence, then this modified sequence becomes the candidate sequence, the placements of the blocks for the allocation being those of the placement sequence defined as a candidate sequence once each modified sequence has been developed.

Abstract: A dual-model memory interface of a computing system is provided, configurable to present memory interfaces having differently-graded bandwidth capacity to different processors of the computing system. A mode switch controller of the memory interface controller, based on at least an arbitration rule written to a configuration register, switches the memory interface controller between a narrow-band mode and a wide-band mode. In each mode, the memory interface controller disables either a plurality of narrow-band memory interfaces of the memory interface controller according to a first bus standard, or a wide-band memory interface of the memory interface controller according to a second bus standard. The memory interface controller virtualizes a plurality of system memory units of the computing system as a virtual wide-band memory unit according to the second bus standard, or virtualizes a system memory unit of the computing system as a virtual narrow-band memory unit according to the first bus standard.

Abstract: Broadly speaking, embodiments of the present technique provide apparatus and methods for improved wear-levelling in (volatile and non-volatile) memories. In particular, the present wear-levelling techniques comprise moving static memory states within a memory, in order to substantially balance writes across all locations within the memory.

Abstract: A data storage apparatus includes a storage including a plurality of planes, which include a plurality of pages, and a controller configured to control the storage to read data by grouping the plurality of pages as a page group in an interleaving unit, manage pages in which valid data are stored, among the plurality of pages, as a first bitmap table, and manage a second bitmap table generated by compressing the first bitmap table in a page group unit.

Abstract: Techniques for computer memory management are disclosed herein. In one embodiment, a method includes in response to receiving a request for allocation of memory, determining whether the request is for allocation from a first memory region or a second memory region of the physical memory. The first memory region has first memory subregions of a first size and the second memory region having second memory subregions of a second size larger than the first size of the first memory region. The method further includes in response to determining that the request for allocation of memory is for allocation from the first or second memory region, allocating a portion of the first or second multiple memory subregions of the first or second memory region, respectively, in response to the request.

Abstract: An arithmetic processor includes a memory access controller configured to control access of a memory based on a memory access request. The memory access controller includes a shift register configured to shift a resource number and a memory access request from a first stage to a subsequent stage of the first stage at a timing according to the operation mode, the first stage is received a resource number and a memory access request. The memory access controller includes a plurality of memory access transmitting circuits configured to receive the resource number and the memory access request held by the plurality of stage. Each of the plurality of access transmitting circuits provided corresponding to the plurality of resource number, and output, to the memory, an access command corresponding to the memory access request when the received resource number matches a resource number of a memory access transmitting circuit.

Abstract: The present technology relates to an electronic system including a host and a memory system. The host includes a request merge manager configured to generate one or more operation request sets, a first request set queue configured to store one or more of transmission request sets and operation request sets, a first scheduler configured to control the priorities of the operation request sets and the transmission request sets, a second request set queue configured to store the operation request sets sequentially output from the first request set queue, a second scheduler configured to generate a transmission request set, and a request set detector configured to transmit, to the first scheduler, request information on a request set having a highest priority.

Abstract: A processor of a memory sub-system can select a data retention profile from among a plurality of data retention profiles corresponding to the memory device. The processor can also adjust a wear life indicator based on the selected data retention profile.

Abstract: An apparatus comprises at least one processing device. The at least one processing device is configured to detect a write pressure condition by identifying at least a first set of one or more logical storage devices having a first service level objective for which at least one performance metric has a value that exceeds a specified threshold, and responsive to the detected write pressure condition, to identify at least a second set of one or more logical storage devices, having a second service level objective that is lower than the first service level objective, and that are contributing to the detected write pressure condition. The at least one processing device is further configured, for each of the identified logical storage devices of the second set, to provide a write pressure indication to control throttling of write operations directed to that logical storage device of the second set.

Abstract: Embodiments of the disclosure provide methods and systems for memory management. The method can include: receiving a request for allocating target node data to a memory space, wherein the memory space includes a buffer and an external memory and the target node data comprises property data and structural data and represents a target node of a graph having a plurality of nodes and edges; determining a node degree associated with the target node data; allocating the target node data to the memory space based on the determined node degree.

Abstract: A non-volatile memory express (NVMe) switch is located in between a host and storage. A first storage access command is received from a host via a peripheral computer interface express (PCIe) interface to access the storage. The first storage access command conforms to NVMe and the storage comprises two or more solid-state drives (SSDs). A respective second storage access command is sent to the two or more SSDs based on the first storage access command. A respective completion is received from each of the two or more SSDs based on the respective second storage access command. A completion is sent to the host via the PCIe interface based on the received completions from each of the two or more SSDs.

Abstract: There is provided a method for managing a solid state storage system with hybrid storage technologies. The method includes monitoring one or more storage request streams to identify operating mode characteristics therein from among a set of possible operating mode characteristics. The set of possible operating mode characteristics correspond to a set of available operating modes of the hybrid storage technologies. The method further includes identifying a current operating mode from among the set of available operating modes responsive to the identified operating mode characteristics. The method also includes predicting a likely future operating mode responsive to variations in workload requirements to generate at least one future operating mode prediction. The method additionally includes controlling at least one of data placement, wear leveling, and garbage collection, responsive to the at least one future operating mode prediction.

Abstract: The present application relates to a data processing method for a numerical control system, a computer device and a storage medium. The method comprises: receiving a data request, the data request carrying a target data identifier; parsing the data request to obtain an interactive type corresponding to the target data identifier; when the interactive type corresponding to the target data identifier is a type corresponding to real-time data, searching for data corresponding to the target data identifier in a shared memory of the numerical control system; transferring the data corresponding to the target data identifier from the shared memory to a data cache of the numerical control system and outputting the data.

Abstract: A method, computer program product, and computing system for receiving, via a storage processor of a storage system, a write request for writing a data portion to a storage array enclosure of non-volatile memory express (NVMe) drives communicatively coupled to the storage processor, where the write request may be received from a host. The data portion may be written to a persistent memory write cache within the storage array enclosure.

Abstract: Systems and methods data storage device performance prediction based on garbage collection resources are described. The data storage device may process host storage operations and determine a valid fragment count parameter for a current or future data block. Based on the valid fragment count parameter a predicted performance value for host storage operations is determined and the host device is notified of the predicted performance value.

Abstract: According to one embodiment, a magnetic disk device includes a first disk, a second disk, a first head, a second head, a first actuator including the first head, a second actuator including the second head, a first arithmetic unit executing a first reordering process of a command stored in a first queue corresponding to the first actuator, and a second arithmetic unit executing a second reordering process of a command stored in a second queue corresponding to the second actuator, the first arithmetic unit executing the second reordering process, the second arithmetic unit executing the first reordering process.

Abstract: A data storage device including, in one implementation, a NAND memory and a controller. The NAND memory includes a read/write circuit configured to determine and store initial physical column addresses for each plane included in the NAND memory. The controller is configured to send a read-transfer command and a one-byte address to the NAND memory. The read/write circuit is also configured to retrieve a first initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the one-byte address from the controller. The first initial physical column address is associated with a die address and a plane address included in the one-byte address. The read/write circuit is further configured to retrieve a first set of data stored at the first initial physical column address. The read/write circuit is also configured to output the first set of data to the controller.

Abstract: Methods and systems for a networked storage system are provided. One method includes: utilizing, by a first node, a storage location cache to determine if an entry associated with a first read request for data stored using a logical object owned by a second node configured as a failover partner node of the first node exists; transmitting, by the first node, the first read request to the second node; receiving, by the first node, a response to the first read request from the second node with requested data; inserting, by the first node, an entry in the storage location cache indicating the storage location information for the data; and utilizing, by the first node, the inserted entry in the storage location cache to determine storage location of data requested by a second read request received by the first node.

Abstract: Techniques for managing memory involve: determining a set of weights corresponding to a plurality of command queues in the memory, each weight indicating the number of commands allowed to be transmitted in a corresponding command queue; detecting whether a transmission delay occurs in the plurality of command queues; and adjusting the set of weights based on a result of the detection. Accordingly, transmission and processing efficiencies of commands in a command queue can be improved, and transmission bandwidth can be used more efficiently.

Abstract: An apparatus for operating an input/output (I/O) interface in a virtual machine is provided. The apparatus is configured to: map a first portion of a memory device to a configuration space of an I/O interface; obtain a first mapping table that maps a set of host space virtual addresses to a first set of physical addresses associated with the first portion of the memory device; obtain a second mapping table that maps a second set of physical addresses associated with a second portion of the memory device accessible by a virtual machine to the set of host space virtual addresses; generate a third mapping table that maps the second set of physical addresses to the first set of physical addresses; and provide the third mapping table to a device driver operating in the virtual machine, to enable the device driver to access the configuration space of the I/O interface.