Abstract: Techniques are provided for managing metadata of a storage system. A storage control system manages a storage metadata structure which comprises metadata items for accessing data items in a storage system comprising a persistent write cache and a primary storage. The storage metadata structure comprises a first metadata structure that is configured to organize metadata items received from the write cache at a first granularity, and a second metadata structure that is configured to organize metadata items received from the first metadata structure at a second granularity, wherein the second granularity is greater than the first granularity. The storage control system utilizes the storage metadata structure to access data items in the persistent write cache and the primary storage.

Abstract: Methods, systems, and devices for cache architectures for memory devices are described. For example, a memory device may include a main array having a first set of memory cells, a cache having a second set of memory cells, and a cache delay register configured to store an indication of cache addresses associated with recently performed access operations. In some examples, the cache delay register may be operated as a first-in-first-out (FIFO) register of cache addresses, where a cache address associated with a performed access operation may be added to the beginning of the FIFO register, and a cache address at the end of the FIFO register may be purged. Information associated with access operations on the main array may be maintained in the cache, and accessed directly (e.g., without another accessing of the main array), at least as long as the cache address is present in the cache delay register.

Abstract: Various implementations described herein are directed to device. The device may include a first tier having a processor and a first cache memory that are coupled together via control logic to operate as a computing architecture. The device may include a second tier having a second cache memory that is coupled to the first cache memory. Also, the first tier and the second tier may be integrated together with the computing architecture to operate as a stackable cache memory architecture.

Abstract: Methods, systems, and devices for mapping descriptors for read operations are described. A memory device may include a first cache may include a mapping table between the logical addresses and the physical addresses, and a second cache may include one or more descriptors of one or more physical addresses of the memory array. A descriptor may include a starting logical address, a starting physical address, and a quantity of addresses in the descriptor, and may be configured to identify addresses or sets of address that are frequently accessed. When an access command (e.g., a read command) is received, the first cache may be queried and then the second cache may be queried (if there is a cache miss at the first cache). The physical address of the data of the memory array may be determined (and accessed) based on the descriptors stored in the second cache.

Abstract: Techniques are disclosed relating to cache footprint management. In some embodiments, execution circuitry is configured to perform operations for instructions from multiple threads in parallel. Cache circuitry may store information operated on by threads executed by the execution circuitry. Scheduling circuitry may arbitrate among threads to schedule threads for execution by the execution circuitry. Tracking circuitry may determine one or more performance metrics for the cache circuitry. Control circuitry may, based on the one or more performance metrics meeting a threshold, reduce a limit on a number of threads considered for arbitration by the scheduling circuitry, to control a footprint of information stored by the cache circuitry. Disclosed techniques may advantageously reduce or avoid cache thrashing for certain processor workloads.

Abstract: Techniques of implementing software filtered non-volatile memory in a computing device are disclosed herein. In one embodiment, a method includes detecting an entry being written to a guest admin submission queue (gASQ) by a memory driver of a virtual machine hosted on the computing device. Upon detecting the entry written to the gASQ by the memory driver, the command in the entry is analyzed to determine whether the command is allowed based on a list of allowed or disallowed commands. In response to determining that the command in the entry is not allowed, without sending the command to the non-volatile memory, generating an execution result of the command in response to the entry being written to the gASQ by the memory driver. As such, potentially harmful commands from the memory driver are prevented from being executed by the non-volatile memory.

Abstract: A data storage system can employ a read destructive memory configured to fill a first cache with a first data set from a data repository prior to populating a second cache with a second data set describing the first data set with the first and second cache each having non-volatile ferroelectric memory cells. An entirety of the first cache may be read in response to a cache hit in the second cache with the cache hit responsive to a data read command from a host and with the first cache being read without a refresh operation restoring the data of the first cache.

Abstract: An onboard relay device comprises memory and a processor connected to the memory. The processor is configured to receive a data transmission request from a request originator, determine whether received data that is data received from a transmission originator is variable data or fixed data, record the received data in a cache memory section temporarily in cases in which the received data is the fixed data, determine whether or not transmission request data that is data subject to a transmission request from the request originator is recorded in the cache memory section, and in cases in which the processor has determined the transmission request data to be the received data recorded in the cache memory section, transmit the received data recorded in the cache memory section to the request originator as the transmission request data.

Abstract: A cache purge simulation system includes a device under test with a cache skip switch. A first cache skip switch includes a configurable state register to indicate whether all of an associated cache is purged upon receipt of a cache purge instruction from a verification system or whether a physical partition that is smaller than the associated cache is purged upon receipt of the cache purge instruction from the verification system. A second cache skip switch includes a configurable start address register comprising a start address that indicates a beginning storage location of a physical partition of an associated cache and a configurable stop address register comprising a stop address that indicates a ending storage location of the physical partition of the associated cache.

Abstract: A device includes: a first interface circuit configured to communicate with a host processor; a second interface circuit configured to communicate with a memory comprising a plurality of storage regions; a cache memory including a plurality of cache lines configured to temporarily store data; and a controller configured to receive an integrated command from the host processor, the integrated command comprising memory operation information and cache management information, configured to control the memory based on a first command that is instructed according to the memory operation information, and configured to control at least one of the plurality of cache lines based on the cache management information.

Abstract: A request to generate a storage system model is received. The storage system model represents at least a portion of a storage system. In response to receiving the request, a storage system interface configuration is loaded. The storage system interface configuration comprises an attribute of an entity model. The attribute corresponds to an attribute of a storage system entity of the storage system. Further in response to receiving the request, the entity model is identified as representing the storage system entity. In response to identifying the entity model as representing the storage system entity, the entity model is instantiated.

Abstract: An apparatus and method for handling stash requests are described. The apparatus has a processing element with an associated storage structure that is used to store data for access by the processing element, and an interface for coupling the processing element to interconnect circuitry. Stash request handling circuitry is also provided that, in response to a stash request targeting the storage structure being received at the interface from the interconnect circuitry, causes a block of data associated with the stash request to be stored within the storage structure. The stash request identifies a given address that needs translating into a corresponding physical address in memory, and also identifies an address space key. Address translation circuitry is used to convert the given address identified by the stash request into the corresponding physical address by performing an address translation that is dependent on the address space key identified by the stash request.

Abstract: A storage system allocates single-level cell (SLC) blocks in its memory to act as a write buffer. A host sends the storage system a threshold indicating an amount of data that should be stored in the write buffer before the storage system flushes the write buffer to multi-level cell (MLC) blocks in the memory. Using this threshold can extend the amount of time that data is maintained in the write buffer, which can reduce the write-amplification factor and power consumption, as well as increase read performance of the data.

Abstract: Techniques for performing cache operations are provided. The techniques include, recording an entry indicating that a cache line is exclusive-upgradeable; removing the cache line from a cache; and converting a request to insert the cache line into the cache into a request to insert the cache line in the cache in an exclusive state.

Abstract: A method and a computer program product executed by a processor may include or perform various operations. The operations include periodically reading a wear level for each of a plurality of storage devices operating in a multi-tiered storage system which includes a first storage tier and a second storage tier that is a lower tier than the first storage tier. At least one storage device operates in the first storage tier and at least one storage device operates in the second storage tier. The operations further include identifying a first storage device of the plurality of storage devices that is operating in the first storage tier and has a wear level that is higher than an average wear level for the plurality of storage devices. The operations additionally include causing the first storage device to switch from operating in the first storage tier to operating in the second storage tier.

Abstract: Data segments and metadata segments to be stored in a storage system, where the data segments are deduplicated segments and each of the metadata segments includes a fingerprint for the corresponding data segment, for each of the metadata segments. It is determined that the metadata segment contains one or markers inserted by a client device of the storage system. The metadata segment is examined to determine whether the metadata segment satisfies a predetermined condition. In response to determining that the metadata satisfies the predetermined condition, the metadata segment is compressed using a predetermined compression algorithm. The compressed metadata segment is stored in the storage system, otherwise the metadata segment is stored in the storage system without compression. Thereafter, the data segments are stored in the storage system.

Abstract: The disclosed embodiments relate to per-process configuration caches in storage devices. A method is disclosed comprising initiating a new process, the new process associated with a process context; configuring a region in a memory device, the region associated with the process context, wherein the configuring comprises setting one or more cache parameters that modify operation of the memory device; and mapping the process context to the region of the memory device.

Abstract: Techniques for cache management involve: determining respective elimination scores of a plurality of entries in a cache based at least in part on compression rates of data blocks corresponding to the plurality of entries, the elimination score being proportional to the compression rate; and removing, from the cache, at least one entry with a relatively low elimination score among the plurality of entries. Such techniques are able to optimize the retention and elimination strategies for entries in a cache, thus increasing payoffs for using the cache.

Abstract: A method for migration of data is provided. The method includes triggering a rebuild of data according to a first migration mechanism from a first storage drive to a second storage drive. Monitoring space utilization associated with the second storage drive, and adaptively switching the migration of the data from the first migration mechanism to a second migration mechanism based on the monitoring.

Abstract: A multi-purpose server cache directory in a computing environment is provided. One of a plurality of operation modes may be selectively enabled or disabled, by a cache directory, based on a computation phase, data type, and data pattern for caching data in a cache having a plurality of address tags in the cache directory greater than a number of data lines in a cache array.