Abstract: Methods, systems, and devices for cache architectures for memory devices are described. For example, a memory device may include a main array having a first set of memory cells, a cache having a second set of memory cells, and a cache delay register configured to store an indication of cache addresses associated with recently performed access operations. In some examples, the cache delay register may be operated as a first-in-first-out (FIFO) register of cache addresses, where a cache address associated with a performed access operation may be added to the beginning of the FIFO register, and a cache address at the end of the FIFO register may be purged. Information associated with access operations on the main array may be maintained in the cache, and accessed directly (e.g., without another accessing of the main array), at least as long as the cache address is present in the cache delay register.

Abstract: A method of processing and storing general data by means of hardware obtains initial unhashed data and a fixed value. If a value of the initial unhashed data is greater than the fixed value, the initial data is divided into N sub-data or segments. A size of each sub-data is not more than the fixed value, N being an integer greater than 1. The collection of sub sets of data is input into a memory of the electronic device after hashing.

Abstract: Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.

Abstract: A method for updating software of storage units of a set of storage units in a storage network. In an embodiment, each storage unit of the set of storage units determines a data slice storage status for data slices stored in the storage unit (e.g., by monitoring rebuilding messages relating to the data slices). A processing module of the storage network obtains the data slice storage status of the storage units of the set of storage units and determines whether to perform a software update to software of the storage units of the set of storage units. Determining whether to perform the software update includes determining, based on the data slice storage status of the storage units, whether a threshold number of storage units are associated with a favorable data slice storage status. In response to determining that a threshold number of storage units are associated with a favorable data slice storage status, the processing module indicates to perform the software update.

Abstract: An information processing apparatus includes a processor. The processor configured to allocate, to a process, a first number of first divided regions from among a plurality of divided regions obtained by division of a cache, and determine, based on an address of each data block corresponding to the process and the first number, a storage destination of the data block corresponding to the process from among the first divided regions. The processor configured to determine a second number that is a divisor of the first number, identify, for the individual first divided regions after the reduction, second divided regions from among the first divided regions before the reduction, determine data blocks to be stored in the individual first divided regions after the reduction by allocating data blocks to the first divided regions after the reduction from the corresponding second divided regions in ascending order of purging order.

Abstract: The present disclosure describes technologies and techniques for use by a data storage controller—such as a controller for use with a NAND or other non-volatile memory (NVM)—to provide a user-expandable memory space. In examples described herein, a customer may choose to purchase access to only a portion of the total available memory space of a consumer device, such as a smartphone. Later, the customer may expand the user-accessible memory space. In one example, the customer submits suitable payment via a communication network to a centralized authorization server, which returns an unlock key. Components within the data storage controller of the consumer device then use the key to unlock additional memory space within the device. In this manner, if the initial amount of memory the consumer paid for becomes full, the consumer may conveniently expand the amount of user-accessible memory.

Abstract: A nonvolatile memory includes a memory array, a sensor for measuring a temperature, an interface through which a write command is to be received, and a control circuit. The control circuit is configured to write information of the temperature measured by the sensor in a data storing area of the memory array in which user data associated with the write command is not capable of being written into, when writing the user data in the memory array in response to the received write command.

Abstract: Techniques to back up data are disclosed. In various embodiments, a function pointer associated with a system call by an application is modified to point to a custom write function. A request to write application data is received at the custom write function. The application data is written to a backup destination based at least in part on a determination that the request is associated with invocation of a backup method of the application.

Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which storage in the memory device is managed. An allocation can include conducting a garbage collection procedure to free up one or more blocks. In various embodiments, execution of a garbage collection procedure can be based on operation of two tables with respect to a logical to physical mapping table split into logical to physical mapping table regions saved in the memory device. The first table can maintain counts of valid pages in blocks for a logical to physical mapping table region. The second table can include bits to identify logical to physical mapping table regions involved in the garbage collection procedure based on the entries in the first table. Search of the second table can determine logical to physical mapping table regions involved in the garbage collection. Additional apparatus, systems, and methods are disclosed.

Abstract: Each controller moves authority for access processing to data in a logical area allocated to the controller between the controllers, for a first storage area in which there is data related to the logical areas of the plurality of controllers by moving the authority for the access processing from a first controller to a second controller. Each of the first controller and the second controller writes data after update related to a write request to the storage area allocated to the own controller and deletes data before update in the first storage area, and moves data for which the own controller has the authority for the access processing in the first storage area to another storage area allocated to the own controller while taking over the allocation of the first storage area in relocation processing of relocating data.

Abstract: A storage device includes a memory device and a controller. The memory device stores attribute information associated with a host memory buffer allocated on a host memory. The controller communicates with the host memory such that a plurality of pieces of data associated with operations of the memory device is buffered, based on the attribute information, in a plurality of host memory buffers allocated on the host memory. The controller communicates with the host memory such that first data corresponding to a first attribute group managed in the attribute information is buffered in a first host memory buffer among the plurality of host memory buffers and second data corresponding to a second attribute group different from the first attribute group is buffered in a second host memory buffer separate from the first host memory buffer.

Abstract: Systems and methods are described for providing rapid access to data sets used by serverless function executions. Rather than pre-loading an entire data set into an environment of a serverless function, which might incur large latencies, the environment is provided with a local access view of the data set, such as in the form of a read-only mount point. As blocks within the data set are requested, a local process can translate the requests into requests for corresponding network objects. The network objects are then retrieved, and the relevant portion of the object is made available to the environment. Network objects may be shared among multiple data sets, so a host device may include a cache enabling an object retrieved for a first environment to also be used to service requests from a second environment.

Abstract: Techniques of implementing software filtered non-volatile memory in a computing device are disclosed herein. In one embodiment, a method includes detecting an entry being written to a guest admin submission queue (gASQ) by a memory driver of a virtual machine hosted on the computing device. Upon detecting the entry written to the gASQ by the memory driver, the command in the entry is analyzed to determine whether the command is allowed based on a list of allowed or disallowed commands. In response to determining that the command in the entry is not allowed, without sending the command to the non-volatile memory, generating an execution result of the command in response to the entry being written to the gASQ by the memory driver. As such, potentially harmful commands from the memory driver are prevented from being executed by the non-volatile memory.

Abstract: An approach to creating a tamper-resistant field programmable gate array (FPGA) and remotely reprogramming the tamper-resistant FPGA. In one aspect, determining if an encryption key is stored in a physical unclonable function (PUF) of the FPGA. Further, responsive to the encryption key not being stored in a PUF, writing an encryption key in tamper resistant memory associated with a back end of the line (BEOL) of the FPGA. In another aspect, writing a program key and a look-up table (LUT) in the tamper resistant memory.

Abstract: Disclosed are a memory system, a memory controller, and a method of operating the memory system. The memory system may configure a plurality of map cache pools for caching map data of different types, respectively, within a map cache in which the map data is cached, configure a timer in a first map cache pool among the plurality of map cache pools, and write map data cached in the first map cache pool in the memory device based on the timer.

Abstract: Only data with a high access frequency is registered to a cache storage. A cache storage stores part of data stored in a main storage. A cache management unit holds an access frequency for each cache entry in the cache storage. A candidate cache management unit holds the access frequency for each candidate entry not registered to the cache storage. A cache update unit updates the access frequency according to an address of an issued access command and updates the cache entry and the candidate entry based on the access frequency.

Abstract: Data is copied, to a first group of data blocks in a first plurality of groups of unmapped data blocks, from a second group of data blocks in a second plurality of groups of mapped data blocks. Upon copying data to the first group of data blocks from the second group of data blocks, the first group of data blocks is included in the second plurality of groups of mapped data blocks. Upon including the first group of data blocks in the second plurality of groups of mapped data blocks, a wear leveling operation is performed on the first group of data blocks, wherein performing the wear leveling operation comprises determining a base address of the first group of data blocks, the base address indicating a location at which the first group of data blocks begins. A request to access subsequent data at a logical address associated with a data block included in the first group of data blocks is received.

Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The memory includes a memory cell array. The controller is configured to control a transfer phase in which a command, an address, and first data are transferred to the memory, and a program phase in which the first data is programmed into the memory cell array by the memory after the transfer phase. The controller is configured to suspend the transfer phase after initiating the transfer phase before completion of the transfer phase, then read second data from the memory, and resume the transfer phase after reading of the second data is completed.

Abstract: A memory system includes a nonvolatile memory apparatus, and a write-same manager configured to perform a write-same operation on the nonvolatile memory apparatus, wherein the write-same manager merges a first write-same operation and a second write-same operation by comparing first operation information of the first write-same operation and second operation information of the second write-same operation.

Abstract: A method for migration of data is provided. The method includes triggering a rebuild of data according to a first migration mechanism from a first storage drive to a second storage drive. Monitoring space utilization associated with the second storage drive, and adaptively switching the migration of the data from the first migration mechanism to a second migration mechanism based on the monitoring.