Patents Examined by Trang K Ta
  • Patent number: 11061568
    Abstract: An access operation performed by a tape drive is detected. The access operation is performed on a tape medium. The access operation has one or more performance characteristics. The performance characteristics of the detected access operation are compared with one or more predefined performance thresholds. The comparison is in response to detecting the access operation. An operation performance of the tape medium is determined. The determination is based on comparing the performance characteristics with the predefined performance thresholds. A table associated with the tape medium is updated based on the operational performance of the tape medium. The table is stored in a non-volatile storage.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: July 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Marcus Breuer, Frank Krick, Bernd Freitag, Tim Oswald
  • Patent number: 11048437
    Abstract: A processing device in a memory system provides an execution grant to a first queue of a plurality of queues, the first queue storing a first plurality of memory commands to be executed on the memory component. The processing device further determines whether a number of commands from the first queue that have been executed since the first queue received the execution grant satisfies an executed transaction threshold criterion and whether a number of pending commands in a second queue of the plurality of queues satisfies a promotion threshold criterion, the second queue storing a second plurality of memory commands to be executed on the memory component. Responsive to at least one of the executed transaction threshold criterion or the promotion threshold criterion being satisfied, the processing device provides the execution grant to the second queue.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: June 29, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jiangli Zhu, Wei Wang, Ying Yu Tai, Jason Duong, Chih-Kuo Kao
  • Patent number: 11042305
    Abstract: According to one embodiment, a memory system manages wear of each of a plurality of blocks in a nonvolatile memory. The memory system receives, from a host, a write request including a parameter specifying a data retention term required for first data to be written. The memory system selects, from the blocks, a first block in which a data retention term estimated from the wear of the first block is longer than or equal to the specified data retention term. The memory system writes the first data to the first block.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: June 22, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Shinichi Kanno, Hideki Yoshida
  • Patent number: 11036411
    Abstract: Apparatuses and techniques are described for more efficiently allocating blocks of data in a memory device. The number of dedicated single-level cell (SLC) blocks which are allocated at the time of manufacture of a memory device can be reduced by transitioning a portion of the multi-level cell (MLC) blocks to an SLC mode at various times in the lifetime of the memory device. In one approach, separate counts are maintained for an MLC block in the SLC and MLC modes. The separate counts can be used to select an MLC block to transition to the SLC mode, or to select an MLC block to program. In another approach, a single count is maintained, where the SLC cycles are weighted less heavily than the MLC cycles.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: June 15, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Narendhiran Chinnaanangur Ravimohan, Muralitharan Jayaraman, Arun Thandapani, Ramkumar Ramamurthy
  • Patent number: 11010209
    Abstract: Disclosed aspects relate to speculative execution management in a coherent accelerator architecture. A first access request from a first component may be detected with respect to a set of memory spaces of a single shared memory in the coherent accelerator architecture. A second access request from a second component may be detected with respect to the set of memory spaces of the single shared memory in the coherent accelerator architecture. The first and second access requests may be processed by a speculative execution management engine using a speculative execution technique with respect to the set of memory spaces of the single shared memory in the coherent accelerator architecture.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: May 18, 2021
    Assignee: International Business Machines Corporation
    Inventors: Pengfei Gou, Yang Liu, Yangfan Liu, Zhenpeng Zuo
  • Patent number: 10976947
    Abstract: A system includes a solid-state storage array having a plurality of solid-state storage devices and a storage controller coupled to the solid-state storage array, the storage controller including a processing device, the processing device to select a segment height based on erase block sizes of the plurality of solid-state storage devices. The processing device is further to program a data segment using the segment height to a data stripe across two or more of the plurality of solid-state storage devices and store the segment height in metadata associated with the data segment.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: April 13, 2021
    Assignee: Pure Storage, Inc.
    Inventors: Andrew R. Bernat, Radek Aster, Benjamin Scholbrock, Conner Haffner, Yunpeng Duan, John Adler, Tsu-Hao Chang
  • Patent number: 10963387
    Abstract: A scheme referred to as a “Region-based cache restoration prefetcher” (RECAP) is employed for cache preloading on a partition or a context switch. The RECAP exploits spatial locality to provide a bandwidth-efficient prefetcher to reduce the “cold” cache effect caused by multiprogrammed virtualization. The RECAP groups cache blocks into coarse-grain regions of memory, and predicts which regions contain useful blocks that should be prefetched the next time the current virtual machine executes. Based on these predictions, and using a simple compression technique that also exploits spatial locality, the RECAP provides a robust prefetcher that improves performance without excessive bandwidth overhead or slowdown.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: March 30, 2021
    Assignee: International Business Machines Corporation
    Inventors: Harold W. Cain, III, Vijayalakshmi Srinivasan, Jason Zebchuk
  • Patent number: 10965316
    Abstract: One embodiment provides a method comprising receiving an input data stream, partitioning the input data stream into a plurality of data blocks, and compressing the data blocks utilizing a plurality of processor sets. Each processor set is assigned a data block to compress. The processor sets compress in parallel to exploit inter-block parallelism. Each processor set comprises one or more processors that collaborate in compressing an assigned data block to exploit intra-block parallelism. The method further comprises writing a plurality of compressed data blocks resulting from the compressing to a storage device in encoded form.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: March 30, 2021
    Assignee: International Business Machines Corporation
    Inventors: Tim Kaldewey, Rene Mueller, Evangelia Sitaridi
  • Patent number: 10956043
    Abstract: The present disclosure includes apparatuses and methods for computing reduction and prefix sum operations in memory. A number of embodiments include processing circuitry configured to compute a reduction operation on data stored in a group of memory cells by splitting the data into a plurality of elements, copying each of the plurality of elements into elements that are wider than before being copied, and performing a logical operation associated with the reduction operation on each of the copied elements.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Jeremiah J. Willcock
  • Patent number: 10956068
    Abstract: A data storage device can have one or more timestamps to indicate chronological information associated with data stored in the data storage device. A controller may be connected to a timestamp module and a transducing head to allow a timestamp to be written to a magnetic data storage medium as directed by the timestamp module. The timestamp can consist of chronological information relating to user-generated data stored on the data storage medium.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: March 23, 2021
    Assignee: Seagate Technology LLC
    Inventor: Christopher Nicholas Allo
  • Patent number: 10936242
    Abstract: Causing data in an in-band storage device coupled to a host computing system to be transferred to an out-of-band (OOB) storage device includes coupling the in-band storage device to the OOB storage device, the in-band storage device detecting commands from the host computing system to transfer the data in the in-band storage device to a cloud storage, and the in-band storage device transferring the data in the in-band storage device to the to the OOB storage device in response to receiving a command from the host computing system to transfer the data in the in-band storage device to the cloud storage. The OOB storage device may be coupled to the cloud storage. Causing data in an in-band storage device to be transferred to an OOB storage device may also include causing data stored at the OOB storage device to be transferred to the cloud storage.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: March 2, 2021
    Assignee: EMC IP Holding Company LLC
    Inventor: Douglas E. LeCrone
  • Patent number: 10922019
    Abstract: A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: receiving a plurality of data from a host system, and writing the data into a plurality of first physical programming units; performing a multi-frame encoding according to the plurality of data to generate encoded data, and writing the encoded data into a second physical programming unit; and writing a plurality of first concatenated information related to the encoded data into the plurality of first programming units, respectively.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: February 16, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Chia-Hung Chien, Hsiao-Hsuan Yen
  • Patent number: 10915246
    Abstract: A method, non-transitory computer readable medium, and device that assists with managing cloud storage includes identifying a portion of data in a data unit identified for deletion in the metadata. The identified portion of the data identified for delete is compare to a threshold amount. Deletion of the data unit from a first storage object is deferred when the determined portion of data identified for deletion is less than the threshold amount. A second storage object with a portion of data unmarked for deletion in the data unit is generated when the determined portion of data marked for deletion is equal to the threshold amount, wherein the second storage object has a same identifier as the first storage object.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: February 9, 2021
    Assignee: NETAPP, INC.
    Inventors: Benjamin Bradford Andken, Sumeeth Channaveerappa Kyathanahalli, Sharad Jain
  • Patent number: 10915244
    Abstract: Communicating data with a medium is provided. A cache is provided for storing target data of a file identified by an access request from an application of a host. The cache is divided into a read cache, a write cache, and an index cache. Responsive to receiving the access request: the medium is loaded onto a drive using a file system; target data is stored to the write cache and to the read cache; and the index file stored in the index cache is updated to reflect position metadata about the target data stored in the write cache. Responsive to initiating unloading of the medium from the drive: the updated index file stored in the index cache is written to the index partition of the medium; and the target data stored in the write cache is written onto a data partition of the medium without using the file system.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: February 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ashida, Tohru Hasegawa, Hiroshi Itagaki, Shinsuke Mitsuma, Terue Watanabe
  • Patent number: 10908820
    Abstract: A high-bandwidth memory (HBM) system includes an HBM device and a logic circuit. The logic circuit receives a first command from the host device and converts the received first command to a processing-in-memory (PIM) command that is sent to the HBM device through the second interface. A time between when the first command is received from the host device and when the HBM system is ready to receive another command from the host device is deterministic. The logic circuit further receives a fourth command and a fifth command from the host device. The fifth command requests time-estimate information relating to a time between when the fifth command is received and when the HBM system is ready to receive another command from the host device. The time-estimate information includes a deterministic period of time and an estimated period of time for a non-deterministic period of time.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: February 2, 2021
    Inventors: Krishna T. Malladi, Hongzhong Zheng, Robert Brennan
  • Patent number: 10909046
    Abstract: Apparatuses and methods related to computer memory access determination are described. A command can be received at a memory system (e.g., a system with or exploiting DRAM). The command can comprise a memory operation and a plurality of privilege bits. The privilege level or a memory address that is associated with the memory operation can be identified. The privilege level can correspond to the memory address can describe a privilege level that can access the memory address. A determination can be made as to whether the memory operation, or the application requesting certain data or prompting corresponding instructions, is entitled to access to the memory address using the plurality of privilege bits and the privilege level. Responsive to determining that the memory operation has access to the memory address, the memory operation can be processed.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: February 2, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Richard C. Murphy
  • Patent number: 10878889
    Abstract: A high retention time memory element is described that has dual gate devices. A memory element has a write transistor with a gate having a source coupled to a write bit line, a gate coupled to a write line, and a drain coupled to a storage node, wherein a value is written to the storage node by enabling the gate and applying the value to the bit line, and a read transistor having a source coupled to a read line, a gate coupled to the storage node, and a drain coupled to a read bit line, wherein the value of the storage node is sensed by applying a current to the source and reading the sense line to determine a status of the gate.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: Rafael Rios, Gilbert Dewey, Van H. Le, Jack Kavalieros, Mesut Meterelliyoz
  • Patent number: 10866892
    Abstract: A memory cache controller includes a transaction arbiter circuit and a retry queue circuit. The transaction arbiter circuit may determine whether a received memory transaction can currently be processed by a transaction pipeline. The retry queue circuit may queue memory transactions that the transaction arbiter circuit determines cannot be processed by the transaction pipeline. In response to receiving a memory transaction that is a cache management transaction, the retry queue circuit may establish a dependency from the cache management transaction to a previously stored memory transaction in response to a determination that both the previously stored memory transaction and the cache management transaction target a common address. Based on the dependency, the retry queue circuit may initiate a retry, by the transaction pipeline, of one or more of the queued memory transactions in the retry queue circuit.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: December 15, 2020
    Assignee: Apple Inc.
    Inventors: Sridhar Kotha, Neeraj Parik
  • Patent number: 10866902
    Abstract: Processor, apparatus, and method for reordering a stream of memory access requests to establish locality are described herein. One embodiment of a method includes: storing in a request queue memory access requests generated by a plurality of execution units, the memory access requests comprising a first request to access a first memory page in a memory and a second request to access a second memory page in the memory; maintaining a list of unique memory pages, each unique memory page associated with one or more memory access requests stored the request queue and is to be accessed by the one or more memory access requests; selecting a current memory page from the list of unique memory pages; and dispatching from the request queue to the memory, all memory access requests associated with the current memory page before any other memory access request in the request queue is dispatched.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: December 15, 2020
    Assignee: Intel Corporation
    Inventors: Ishwar S. Bhati, Udit Dhawan, Jayesh Gaur, Sreenivas Subramoney
  • Patent number: 10860247
    Abstract: A data writing method is provided. The method includes receiving a first write command and first data corresponding to the first write command from a host system, wherein the first write command instructs to store the first data into a first logical address; copying the first data into a register, responding to the host system that the first write command is completed, and starting to execute a first program operation to program the first data into a first physical page; and in response to determining that the first program operation is failed, reading the first data from the register according to a logical to physical addresses mapping table and mandatorily programming the first data into a second physical page.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: December 8, 2020
    Assignee: Shenzhen EpoStar Electronics Limited CO.
    Inventors: Heng-Lin Yen, Hung-Chih Hsieh, Tzu-Wei Fang, Yu-Hua Hsiao