Abstract: A processing device access a command to program data to a page in a block of a memory device. The processing device determines whether the page is a last remaining open page in the block. The processing device accesses a list that indicates enablement of a function to apply read level offsets to one or more open blocks in the memory device. The processing device determines the list includes an entry that matches to the block. The entry indicates enablement of the function to apply read level offsets to the block. The processing device disables the function based on determining the page is a last remaining open page in the block. The processing device adds the command to a prioritized queue of commands. The memory device executes commands from the prioritized queue in an order based on a priority level assigned to each command.

Abstract: A memory system includes a memory device and a controller. The memory device includes a plurality of memory blocks, wherein the plurality of memory blocks includes one or more first memory blocks, each storing at least invalid data and one or more second memory blocks, each of which is blank. The controller is configured to determine a time or a period for performing garbage collection to secure an additional second memory block based at least on a transition speed representing a speed in which the second memory blocks is converted to the first memory blocks, the transition speed being determined based on a change between a first count of the first memory blocks and a second count of the second memory blocks.

Abstract: The present disclosure generally relates to more efficient use of a delta buffer. To utilize the delta buffer, an efficiency can be gained by utilizing absolute delta entries and relative delta entries. The absolute delta entry will include the type of delta entry, the L2P table index, the L2P table offset, and the PBA. The relative delta entry will include the type of delta entry, the L2P table offset, and the PBA offset. The relative delta entry will utilize about half of the storage space of the absolute delta entry. The relative delta entry can be used after an absolute delta entry so long as the relative delta entry is for data stored in the same block as the previous delta entry. If data is stored in a different block, then the delta entry will be an absolute delta entry.

Abstract: Apparatus, methods, media and systems for multiple sets of trim parameters are described. A non-volatile memory device may comprise a first register, a second register, a multiplexer, a first set of I/O lines, each coupled to the first register and the multiplexer, each associated with a particular trim set among multiple trim sets stored in the first register, one or more second I/O lines, each coupled to the second register and the multiplexer. The multiplexer is configured to receive a control signal. The multiplexer is configured to output, based on the control signal, a particular trim set among the multiple trim sets to the second register using the one or more second I/O lines.

Abstract: Memory controller systems, methods and apparatus for memory access and scheduling are herein disclosed. In some aspects, a memory controller includes a clock, a first interface to be coupled with a first memory device via a common memory channel, and a second interface to be coupled with a second memory device via the common memory channel. The memory controller also includes a register to store data to store data to indicate an access scheme to process access requests to the first memory device according to a first timing scheme and issue access requests to the second memory device according to a second timing scheme. The memory controller further includes logic to cause the access scheme to be implemented in order to issue access requests to the first memory device or to issue access requests to the second memory device via the common memory channel.

Abstract: A controller, a memory system, and operating methods thereof are disclosed. A memory system includes at least one nonvolatile memory device and a controller configured to control the nonvolatile memory device. The at least one nonvolatile memory device includes a super block including a plurality of way interleaving memory blocks and each of memory cells included in the plurality of way interleaving memory blocks operates in a first mode which stores N-bit (wherein N is a natural number of 2 or more) data. The controller generates a reproduction super block by replacing at least one bad block among the plurality of way interleaving memory blocks included in the super block with a non-way interleaving spare block and sets each of memory cells included in the non-way interleaving spare block to operate in a second mode which stores M-bit (wherein M is a natural number smaller than N) data.

Abstract: Multiprocessor clusters in a virtualized environment conventionally fail to provide memory access security, which is frequently a requirement for efficient utilization in multi-client settings. Without adequate access security, a malicious process may access what might be confidential data that belongs to a different client sharing the multiprocessor cluster. Furthermore, an inadvertent programming error in the code for one client process may accidentally corrupt data that belongs to the different client. Neither scenario is acceptable. Embodiments of the present disclosure provide access security by enabling each processing node within a multiprocessor cluster to virtualize and manage local memory access and only process access requests possessing proper access credentials. In this way, different applications executing on a multiprocessor cluster may be isolated from each other while advantageously sharing the hardware resources of the multiprocessor cluster.

Abstract: Provided are integrated circuits and methods for operating integrated circuits. An integrated circuit can include a plurality of memory banks and an execution engine including a set of execution components. Each execution component can be associated with a respective memory bank and can read from and write to the respective memory bank. The integrated circuit can further include a set of registers each associated with a respective memory bank from the plurality of memory banks. The integrated circuit can further be operable to load to or store from the set of registers in parallel, and load to or store from the set of registers serially. A parallel operation followed by a serial operation enables data to be moved from many memory banks into one memory bank. A serial operation followed by a parallel operation enables data to be moved from one memory bank into many memory banks.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for writing data in one or more storage units. One of the methods includes obtaining an erasing count for each of multiple storage units, wherein the erasing count equals a total count of erasing operations that have been performed on all blocks of the storage unit. The method further includes identifying one or more of the storage units that satisfy one or more conditions associated with writing data, determining a storage unit that has the smallest erasing count among the identified storage units, and writing the data in the determined storage unit.

Abstract: The present invention is directed to computer storage systems and methods thereof. In an embodiment, a memory system comprises a controller module, a nonvolatile memory, and a volatile memory. The controller module operates according to a command and operation table. The command and operation table can be updated to change the way controller module operates. When the command and operation table is updated, the updated table is stored at a predefined location of the nonvolatile memory. There are other embodiments as well.

Abstract: Systems and methods are disclosed comprising receiving first-level L2P table information from a storage system over a communication interface, maintaining a host L2P table on using the received first-level L2P table information, and providing a read command to the storage system for first data associated with a first LBA and a host L2P entry associated with the first data. The host L2P entry can include a physical address of the first LBA on the storage system according to the host L2P table and a physical address of a portion of the L2P table on the storage system associated with the first LBA. Control circuitry of the storage system can validate the physical address of the first LBA from the host L2P entry using the physical address of the portion of the host L2P table associated with the first LBA and the second-level L2P table.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initialize a block family associated with a memory device; initialize a timeout associated with the block family; initializing a low temperature and a high temperature using a reference temperature at the memory device; responsive to programming a block residing on the memory device, associate the block with the block family; and responsive to at least one of: detecting expiration of the timeout or determining that a difference between the high temperature and the low temperature is greater than or equal to a specified threshold temperature value, close the block family.

Abstract: A storage device comprises a storage medium, storage controller, a host interface, and a bridge slot. The storage controller is configured to control read and write operations to the storage medium and operates according to a firmware written by a storage device manufacturer. The bridge slot is configured to receive a removable bridge storing software written by a third-party different from the storage device manufacturer. The removable bridge is configured to intercept a first command sent from the host system to the storage controller, modify the first command according to the software stored on removable bridge, and transmit the first command to the storage controller.

Abstract: A method of operating a data storage device includes: receiving a single wipe device initialization command from a host, and in response to the wipe device initialization command, executing a wipe device initialization operation that during a single time period initializes the entirety of a mapping table defining logical partitions dividing memory space provided by a physical region of the data storage device.

Abstract: A method at a computing device for data management between a publisher and at least one subscriber, the method including receiving, at a system element, memory requirements from the publisher; creating a memory allocation of a pool of data objects for the publisher based on the received memory requirements; receiving, at the system element, consumption criteria from each of the at least one subscriber; and adjusting the memory allocation of the pool of data objects based on the consumption criteria received from the at least one subscriber.

Abstract: A method for adjusting over provisioning space and a flash device are provided. The flash device includes user storage space for storing user data and over provisioning space for garbage collection within the flash device. The flash device receives an operation instruction, and then performs an operation on user data stored in the user storage space based on the operation instruction. Further, the flash device identifies a changed size of user data after performing the operation. Based on the changed size of data, a target adjustment parameter is identified. Further, the flash device adjusts the capacity of the over provisioning space according to the target adjustment parameter. According to the method, the over provisioning ratio can be dynamically adjusted, thereby, a life of the flash device can be prolonged.

Abstract: An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.

Abstract: Techniques to update a trim parameter in non-volatile memory during either a manufacturing stage or a post-manufacturing stage are described. Trim parameters may be stored in a register located within the memory device that is inaccessible by a host device during a normal mode of operation. Post-manufacturing updates to trim parameters by the host device may be feasible by creating registers located within the memory device that are accessible to the host device to provide information regarding trim parameter setting updates. The memory device may read the information from the registers accessible to the host device to update trim parameters stored in the register inaccessible by the host device. In this manner, the host device may not have a direct access to the trim parameters but still be able to provide an update to the trim parameters by updating an entry of the registers accessible by the host device.

Abstract: A memory module includes a plurality of memory devices; a plurality of data buffers suitable for exchanging data with a memory controller; and a module controller suitable for transferring the data between the memory devices and the data buffers based on a command, an address and a clock provided from the memory controller, calculating delay times for transferring the data according to locations of the data buffers, and controlling times at which the data are transferred based on the calculated delay times.

Abstract: Data may be read from a data storage device using host performance booster (HPB). An encoded HPB entry in a read command provides the PBA (Physical Block Address) as well as the run length. The LBA (Logical Block Address), PBA, and run length are placed in an HPB read buffer table. The HPB read buffer table is located in the host device. When the read command is received by the data storage device, the data storage device reads the LBA, transfer length, and HPB entry from the read command. The HPB entry contains the PBA for the LBA as well as the run length for the data to be read. For non-sequential reads, the HPB contains the LBA, transfer length, and reference to a write buffer table that is stored in the data storage device.