Patents Examined by Trang K Ta
  • Patent number: 10353819
    Abstract: Next line prefetchers employing initial high prefetch prediction confidence states for throttling next line prefetches in processor-based system are disclosed. Next line prefetcher prefetches a next memory line into cache memory in response to read operation. To mitigate prefetch mispredictions, next line prefetcher is throttled to cease prefetching after prefetch prediction confidence state becomes a no next line prefetch state indicating number of incorrect predictions. Instead of initial prefetch prediction confidence state being set to no next line prefetch state, which is built up in response to correct predictions before performing a next line prefetch, initial prefetch prediction confidence state is set to next line prefetch state to allow next line prefetching. Thus, next line prefetcher starts prefetching next lines before requiring correct predictions to be “built up” in prefetch prediction confidence state.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: July 16, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Brandon Dwiel, Rami Mohammad Al Sheikh
  • Patent number: 10353608
    Abstract: A device and method for determining number of storage devices for each of plurality of storage tiers and assignment of data to be stored in the plurality of storage tiers. The device computes an optimized number of storage devices for each tier including a classifier, which receives units as input data to be stored in the system. Based on the characteristics of the storage devices, the device outputs a data-unit-to-storage tier assignment. An optimizer receives data-unit-to-storage tier assignment from the classifier and a cost budget for the system. Thereafter, an output for the number of storage devices for each storage tier is calculated. A method for determining number of storage devices for each of a plurality of storage tiers and assignment of data to be stored in the plurality of storage tiers are also provided.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: July 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ilias Iliadis, Jens Jelitto, Yusik Kim, Slavisa Sarafijanovic, Vinodh Venkatesan
  • Patent number: 10338850
    Abstract: In one embodiment, a solid state storage drive comprises a plurality of flash memory devices configured to store a plurality of data clusters having a predefined data cluster size, and configured to store a first part of a first data cluster of the plurality of data clusters on a first page of flash memory and a second part of the first data cluster on a second page of flash memory, a partial buffer completion bitmap stored in a memory, wherein each bit in the partial buffer completion bitmap corresponds to a location in a buffer configured to receive data clusters read from the plurality of flash memory devices, and a controller configured to cause a page of data to be read from one of the plurality of flash memory devices, the page of data including either the first part of the first data cluster or the second part of the first data cluster, the controller including a queue buffer manager configured to change the status of a bit in the partial buffer completion bitmap when either the first part of the first
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: July 2, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Philip Rose
  • Patent number: 10331348
    Abstract: Communicating data with a medium is provided. A cache is provided for storing target data of a file identified by an access request from an application of a host. The cache is divided into a read cache, a write cache, and an index cache. Responsive to receiving the access request: the medium is loaded onto a drive using a file system; target data is stored to the write cache and to the read cache; and the index file stored in the index cache is updated to reflect position metadata about the target data stored in the write cache. Responsive to initiating unloading of the medium from the drive: the updated index file stored in the index cache is written to the index partition of the medium; and the target data stored in the write cache is written onto a data partition of the medium without using the file system.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ashida, Tohru Hasegawa, Hiroshi Itagaki, Shinsuke Mitsuma, Terue Watanabe
  • Patent number: 10331363
    Abstract: A node includes a controller that includes one or more processors. The controller may be configured to load data from a storage data block of a plurality of storage data blocks stored on one or more first data storage devices to a working data block stored on one or more second data storage devices. In response to a node experiencing a failure, the controller can be configured to determine a change value for the working data block. The controller can be configured to determine whether data stored in the working data block is different than data stored in the corresponding storage data block based on the determined change value and a provided change value that corresponds to the storage data block.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: June 25, 2019
    Assignee: Seagate Technology LLC
    Inventor: Nathaniel Rutman
  • Patent number: 10324850
    Abstract: A cache system is configurable to trade power consumption for cache access latency. When it is desired for a system with a cache to conserve dynamic power, the lookup of accesses (e.g., snoops) to cache tag ways is serialized to perform one (or less than all) tag way access per clock (or even slower). Thus, for an N-way set associative cache, instead of performing a lookup/comparison on the N tag ways in parallel, the lookups are performed one tag way at a time. This take N times more cycles thereby reducing the access/snoop bandwidth by a factor of N. However, the power consumption of the serialized access when compared to ‘all parallel’ accesses/snoops is reduced.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: June 18, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Patrick P. Lai, Robert Allen Shearer
  • Patent number: 10318172
    Abstract: Cache operation in a multi-threaded processor uses a small memory structure referred to as a way enable table that stores an index to an n-way set associative cache. The way enable table includes one entry for each entry in the n-way set associative cache and each entry in the way enable table is arranged to store a thread ID. The thread ID in an entry in the way enable table is the ID of the thread associated with a data item stored in the corresponding entry in the n-way set associative cache. Prior to reading entries from the n-way set associative cache identified by an index parameter, the ways in the cache are selective enabled based on a comparison of the current thread ID and the thread IDs stored in entries in the way enable table which are identified by the same index parameter.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: June 11, 2019
    Assignee: MIPS Tech, LLC
    Inventor: Philip Day
  • Patent number: 10318166
    Abstract: Techniques for preserving locality of storage accesses to copies of storage objects in a cluster of appliances. Mapping metadata is created indicating regions in a copy of a storage object that are mapped to local storage allocated from a target appliance. Read and write operations to regions of the copy that are mapped to storage in the target appliance are processed within the target appliance. Write operations to regions that are not mapped to storage in the target appliance cause storage to be allocated to the copy in the target appliance, mapped to the regions indicated by the write operations, and used to store the write data. Read operations to regions that are not mapped to storage in the target appliance are performed on an original storage object located on a source appliance, from which the copy of the storage object was made.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: June 11, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Himabindu Tummala, Girish Sheelvant, William C. Davenport, Daniel Cummins
  • Patent number: 10318427
    Abstract: An instruction in a first cache line may be identified and an address associated with the instruction may be determined. The address may be determined to cross a cache line boundary associated with the first cache line and a second cache line. In response to determining that the address crosses the cache line boundary, the instruction may be adjusted based on a portion of the address included in the first cache line and a second instruction may be created based on a portion of the address included in the second cache line. The second instruction may be injected into an instruction pipeline after the adjusted instruction.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Ramon Matas, Chung-Lun Chan, Alexey P. Suprun, Aditya Kesiraju
  • Patent number: 10303386
    Abstract: According to one embodiment, a data processing device is described including a non-volatile memory configured to store configuration data for the data processing device, a volatile memory and a control system configured to copy the configuration data from the non-volatile memory to a section of the volatile memory, block writing to the section of the volatile memory and to put the data processing device into a hibernation mode in which the non-volatile memory is inactive and the volatile memory is active.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: May 28, 2019
    Assignee: Infineon Technologies AG
    Inventors: Peter Blicharski, Witold Gora, Leong Kee Chee
  • Patent number: 10268588
    Abstract: A scheme referred to as a “Region-based cache restoration prefetcher” (RECAP) is employed for cache preloading on a partition or a context switch. The RECAP exploits spatial locality to provide a bandwidth-efficient prefetcher to reduce the “cold” cache effect caused by multiprogrammed virtualization. The RECAP groups cache blocks into coarse-grain regions of memory, and predicts which regions contain useful blocks that should be prefetched the next time the current virtual machine executes. Based on these predictions, and using a simple compression technique that also exploits spatial locality, the RECAP provides a robust prefetcher that improves performance without excessive bandwidth overhead or slowdown.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: April 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Harold W. Cain, III, Vijayalakshmi Srinivasan, Jason Zebchuk
  • Patent number: 10261691
    Abstract: The present disclosure includes apparatuses and methods for computing reduction and prefix sum operations in memory. A number of embodiments include processing circuitry configured to compute a reduction operation on data stored in a group of memory cells by splitting the data into a plurality of elements, copying each of the plurality of elements into elements that are wider than before being copied, and performing a logical operation associated with the reduction operation on each of the copied elements.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: April 16, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Jeremiah J. Willcock
  • Patent number: 10261843
    Abstract: Disclosed aspects relate to speculative execution management in a coherent accelerator architecture. A first access request from a first component may be detected with respect to a set of memory spaces of a single shared memory in the coherent accelerator architecture. A second access request from a second component may be detected with respect to the set of memory spaces of the single shared memory in the coherent accelerator architecture. The first and second access requests may be processed by a speculative execution management engine using a speculative execution technique with respect to the set of memory spaces of the single shared memory in the coherent accelerator architecture.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: April 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Pengfei Gou, Yang Liu, Yangfan Liu, Zhenpeng Zuo
  • Patent number: 10261897
    Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include a host interface logic to receive a write command from a host and flash memory to store data. The SSD may also include an SSD controller, which may include storage for a just-in-time threshold and a tail latency threshold flash translation layer. The flash translation layer may invoke a just-in-time garbage collection strategy when the number of free pages on the SSD is less than the just-in-time threshold, and a tail latency-aware garbage collection strategy when the number of free pages is less than the tail latency threshold. The tail latency-aware garbage collection strategy may pair the write command with a garbage collection command.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: April 16, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jongmin Gim, Hongzhong Zheng
  • Patent number: 10248574
    Abstract: Embodiments of apparatuses, methods, and systems for input/output translation lookaside buffer (IOTLB) prefetching are described. In an embodiment, an apparatus includes a bridge, an input/output memory management unit (IOMMU), and an IOTLB prefetch unit. The bridge is between an input/output (I/O) side of a system and a memory side of the system. The I/O side is to include an interconnect on which a zero-length transaction is to be initiated by an I/O device. The zero-length transaction is to include an I/O-side memory address. The IOMMU includes address translation hardware and an IOTLB. The address translation hardware is to generate a translation of the I/O-side memory address to a memory-side memory address. The translation is to be stored in the IOTLB. The IOTLB prefetch control unit includes prefetch control logic to cause the apparatus to, in response to determining that the memory-side address is inaccessible, emulate completion of the zero-length transaction.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Rupin H. Vakharwala, Eric A. Gouldey, Camron B. Rust, Brett Ireland, Rajesh M. Sankaran
  • Patent number: 10248330
    Abstract: A data storage device with one or more buffers can employ buffer tenure management with at least a data storage device having a first buffer, a second buffer, a buffer manager, and a non-volatile memory. The first buffer can be located on-chip while the second buffer is located off-chip. The first buffer may be filled with data having a tenure of less than a predetermined tenure threshold as directed by the buffer manager.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: April 2, 2019
    Assignee: Seagate Technology LLC
    Inventors: Jackson Ellis, Jeffrey Munsil, Timothy Canepa, Stephen Hanna
  • Patent number: 10235085
    Abstract: A method for execution by a dispersed storage and task (DST) processing unit that includes a processor includes generating storage unit heat data based on a plurality of temperature readings received from each of a plurality of storage units, where the storage unit heat data indicates a first hot storage unit. A pair of storage units is selected from the plurality of storage units based on the storage unit heat data, where the pair of storage units includes the first hot storage unit and a second storage unit. A data swap request is generated for transmission to the pair of storage units, where the data swap request includes an instruction to transfer at least one first data slice from the first hot storage unit to the second storage unit and to transfer at least one second data slice from the second storage unit to the first hot storage unit.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: March 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Teague S. Algie, Andrew G. Peake
  • Patent number: 10235288
    Abstract: Systems and techniques for cache management are disclosed that provide improved cache performance by prioritizing particular storage stripes for cache flush operations. The systems and techniques may also leverage features of the storage devices to provide atomicity without the overhead of inter-controller mirroring. In some embodiments, the systems and techniques include a storage controller that stores data in a cache. The data is associated with one or more sectors of a storage stripe that is defined over plurality of storage devices. The storage controller identifies a locality of dirty sectors of the one or more sectors, classifies the storage stripe into a category based on the locality, provides a category ordering of the category relative to at least one other category, and flushes the storage stripe from the cache to the plurality of storage devices according to the category ordering.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: March 19, 2019
    Assignee: NETAPP, INC.
    Inventors: Arindam Banerjee, Donald R Humlicek, Scott Terrill
  • Patent number: 10216455
    Abstract: The disclosed computer-implemented method for performing storage location virtualization may include (i) identifying a volume storage location for an operating-system-level virtualization container that isolates an instance of user space, the volume storage location providing a working space for data accessed during the existence of the operating-system-level virtualization container, (ii) mapping, through an automated driver that performs location virtualization, the volume storage location to multiple distinct source locations outside of the operating-system-level virtualization container, rather than a single source location, and (iii) propagating, through the automated driver, changes to the data within the working space of the volume storage location during the existence of the operating-system-level virtualization container to the respective multiple distinct source locations outside of the operating-system-level virtualization container to preserve the changes.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: February 26, 2019
    Assignee: Veritas Technologies LLC
    Inventors: Ryan Schroeder, Kirk Searls, Aaron Christensen
  • Patent number: 10216412
    Abstract: Operating a data processing system including producing data in the form of plural blocks of data, where each block of data represents a particular region of an output data array, storing the data in a memory of the data processing system, and reading the data from the memory in the form of lines. Storing the data in the memory comprises storing each block of data of a first row of blocks of data in the memory at one or more memory addresses of a first set of memory addresses of a sequence of memory addresses for the memory, and storing each block of data of a second row of blocks of data in the memory at one or more memory addresses of a second set of different memory addresses of the sequence of memory addresses for the memory.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: February 26, 2019
    Assignee: Arm Limited
    Inventor: Sharjeel Saeed