Patents Examined by Trang K Ta
  • Patent number: 10732839
    Abstract: A universal mechanism is utilized for data rebalancing in a scaled-out data storage cluster. A value (l) representing a number of erasure coded fragments of each data portion that are to be moved to a newly added node can be calculated. Initially, the number of erasure coded fragments moved per data fragment is determined based on the greatest integer that is less than or equal to l and remainders are accumulated. When accumulated reminders equal or exceed l, the number of erasure coded fragments moved per data fragment is determined based on the lowest integer that is greater than or equal to l. A value of accumulated reminders is then decreased by l. Accordingly, system-level imbalances can be avoided and data availability, data robustness, and/or overall system performance can be increased.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: August 4, 2020
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mikhail Danilov, Vladislav Eremeev
  • Patent number: 10713081
    Abstract: Secure and efficient memory sharing for guests is disclosed. For example, a host has a host memory storing first and second guests whose memory access is managed by a hypervisor. A request to map an IOVA of the first guest to the second guest is received, where the IOVA is mapped to a GPA of the first guest, which is is mapped to an HPA of the host memory. The HPA is mapped to a second GPA of the second guest, where the hypervisor controls access permissions of the HPA. The second GPA is mapped in a second page table of the second guest to a GVA of the second guest, where a supervisor of the second guest controls access permissions of the second GPA. The hypervisor enables a program executing on the second guest to access contents of the HPA based on the access permissions of the HPA.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: July 14, 2020
    Assignee: RED HAT, INC.
    Inventors: Michael Tsirkin, Stefan Hajnoczi
  • Patent number: 10705758
    Abstract: Apparatus, methods, media and systems for multiple sets of trim parameters are described. A non-volatile memory device may comprise a first register, a second register, a multiplexer, a first set of I/O lines, each coupled to the first register and the multiplexer, each associated with a particular trim set among multiple trim sets stored in the first register, one or more second I/O lines, each coupled to the second register and the multiplexer. The multiplexer is configured to receive a control signal. The multiplexer is configured to output, based on the control signal, a particular trim set among the multiple trim sets to the second register using the one or more second I/O lines.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: July 7, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Tomer Tzvi Eliash, Asaf Gueta, Inon Cohen, Yuval Grossman
  • Patent number: 10698833
    Abstract: A method for supporting a plurality of requests for access to a data cache memory (“cache”) is disclosed. The method comprises accessing a first set of requests to access the cache, wherein the cache comprises a plurality of blocks. Further, responsive to the first set of requests to access the cache, the method comprises accessing a tag memory that maintains a plurality of copies of tags for each entry in the cache and identifying tags that correspond to individual requests of the first set. The method also comprises performing arbitration in a same clock cycle as the accessing and identifying of tags, wherein the arbitration comprises: (a) identifying a second set of requests to access the cache from the first set, wherein the second set accesses a same block within the cache; and (b) selecting each request from the second set to receive data from the same block.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: June 30, 2020
    Assignee: Intel Corporation
    Inventors: Karthikeyan Avudaiyappan, Sourabh Alurkar
  • Patent number: 10691376
    Abstract: A computer-implemented method according to one embodiment includes identifying code word interleaved (CWI)-4 entries to be re-written to a data storage cartridge, selecting a subset of the CWI-4 entries to be included within a first CWI-4 set, where a plurality of the CWI-4 entries within the subset are associated with a single sub data set (SDS), and re-writing the first CWI-4 set to the data storage cartridge.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: June 23, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kevin D. Butt, Roy D. Cideciyan, Simeon Furrer, Mark A. Lantz
  • Patent number: 10691542
    Abstract: According to an embodiment, a storage device includes a plurality of memory nodes and a control unit. Each of the memory nodes includes a storage unit including a plurality of storage areas having a predetermined size. The memory nodes are connected to each other in two or more different directions. The memory nodes constitute two or more groups each including two or more memory nodes. The control unit is configured to sequentially allocate data writing destinations in the storage units to the storage areas respectively included in the different groups.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: June 23, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yuki Sasaki, Takahiro Kurita, Atsuhiro Kinoshita
  • Patent number: 10691344
    Abstract: A first memory controller receives an access command from a second memory controller, where the access command is timing non-deterministic with respect to a timing specification of a memory. The first memory controller sends at least one access command signal corresponding to the access command to the memory, wherein the at least one access command signal complies with the timing specification. The first memory controller determines a latency of access of the memory. The first memory controller sends feedback information relating to the latency to the second memory controller.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: June 23, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Doe Hyun Yoon, Sheng Li, Jichuan Chang, Ke Chen, Parthasarathy Ranganathan, Norman Paul Jouppi
  • Patent number: 10691345
    Abstract: A memory controller method and apparatus, which includes a modification of at least one of a first timing scheme or a second timing scheme based on information about one or more data requests to be included in at least one of a first queue scheduler or a second queue scheduler, the first timing scheme indicating when one or more requests in the first queue scheduler are to be issued to the first memory set via a first memory set interface and over a channel, the second timing scheme indicating when one or more requests in the second queue scheduler are to be issued to the second memory set via a second memory set interface and over the channel. Furthermore, an issuance of a request to at least one of the first memory set in accordance with the modified first timing scheme or the second memory set in accordance with the modified second timing scheme may be included.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: June 23, 2020
    Assignee: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Mark Schmisseur
  • Patent number: 10684961
    Abstract: External memory protection may be implemented for content addressable memory (CAM). Memory protection data, such as duplicate values for entries in a CAM or error detection codes generated from values of the entries in a CAM, may be stored in a random access memory that is separate from the CAM. When an entry in the CAM is accessed to perform a lookup or scrubbing operation, the memory protection data may be obtained from the RAM. A validation of the value of the entry may then be performed according to the memory protection data to determine whether the value is valid.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: June 16, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Kiran Kalkunte Seshadri, Thomas A. Volpe
  • Patent number: 10678479
    Abstract: Provided are integrated circuits and methods for operating integrated circuits. An integrated circuit can include a plurality of memory banks and an execution engine including a set of execution components. Each execution component can be associated with a respective memory bank, and can read from and write to only the respective memory bank. The integrated circuit can further include a set of registers each associated with a respective memory bank from the plurality of memory banks. The integrated circuit can further be operable to load to or store from the set of registers in parallel, and load to or store from the set of registers serially. A parallel operation followed by a serial operation enables data to be moved from many memory banks into one memory bank. A serial operation followed by a parallel operation enables data to be moved from one memory bank into many memory banks.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: June 9, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Ron Diamant, Randy Renfu Huang, Sundeep Amirineni, Jeffrey T. Huynh
  • Patent number: 10649656
    Abstract: Techniques to update a trim parameter in non-volatile memory during either a manufacturing stage or a post-manufacturing stage are described. Trim parameters may be stored in a register located within the memory device that is inaccessible by a host device during a normal mode of operation. Post-manufacturing updates to trim parameters by the host device may be feasible by creating registers located within the memory device that are accessible to the host device to provide information regarding trim parameter setting updates. The memory device may read the information from the registers accessible to the host device to update trim parameters stored in the register inaccessible by the host device. In this manner, the host device may not have a direct access to the trim parameters but still be able to provide an update to the trim parameters by updating an entry of the registers accessible by the host device.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: May 12, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Shekoufeh Qawami, Doyle W. Rivers
  • Patent number: 10635313
    Abstract: An operating method of a semiconductor device and a memory system, each including a multi-connection port, includes: receiving connection information of a first device while connecting to the first device; updating information of a management table by using the connection information; and generating and transmitting a first packet including the connection information of the first device to a second device pre-connected to the memory system.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: April 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Tae Park, Hwa-Seok Oh, Jin-Hyeok Choi
  • Patent number: 10620860
    Abstract: Operations include storing and/or accessing data in tape volume containers. A system receives a request to access a tape block in a data storage tape. The system maps the requested tape block in the data storage tape to an object in a container. The system then retrieves data from the object in the container. The system generates, from the retrieved data, a data stream in tape archive format. The system transmits the data stream, in tape archive format, in response to the request to access the tape block in the data storage tape.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: April 14, 2020
    Assignee: Oracle International Corporation
    Inventors: Benjamin Dischinger, Bradford Blasing, Jeffrey Andre, David Major
  • Patent number: 10621120
    Abstract: An integrated-circuit buffer component includes a control-side data interface configurably coupled to first and second memory-side data interfaces via internal conductors, the first data interface having twice as many input/output (I/O) transceivers as the second data interface. In a first memory system configuration in which only the first data interface is coupled to a memory module, steering circuitry couples all the internal data conductors exclusively to the I/O transceivers of the first data interface. In a second memory system configuration in which the first and second data interfaces are coupled to respective memory modules, the steering circuitry couples a first half of the internal data conductors exclusively to the I/O transceivers of the second data interface while a second half of the internal data conductors remains exclusively coupled to half the I/O transceivers of the first data interface.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: April 14, 2020
    Assignee: Rambus Inc.
    Inventors: Ian P. Shaeffer, Arun Vaidyanath, Sanku Mukherjee
  • Patent number: 10620841
    Abstract: Herein are data storage devices that transfer a reference to a data object during a storage operation. The data storage devices include a host controller configured to obtain a reference of an object stored in a shared memory system for writing to a storage media controlled by a drive controller. The host controller transfers the reference of the object in the memory system to the drive controller. The host controller also transfers a storage command to the drive controller to write the object to the storage media.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: April 14, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Curtis H. Bruner, Christopher J. Squires
  • Patent number: 10614881
    Abstract: Performing a calibration of a NAND flash memory block that is in an open state. An open state of the NAND flash memory block is detected, the NAND flash memory block comprising a plurality of memory pages, each of which comprising a plurality of memory cells. A group of pages of the NAND flash memory block being in an open state having comparable characteristics is identified. A calibration of read voltage values to pages of the group of identified pages is performed.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Nikolaos Papandreou, Roman A. Pletka, Sasa Tomic, Nikolas Ioannou, Charalampos Pozidis, Aaron D. Fry, Timothy Fisher
  • Patent number: 10592431
    Abstract: According to examples, an apparatus may include a processor to address a physical memory having memory sections, in which a first set of memory sections may be shared between processes and a second set of memory sections may be specific to an individual process. The apparatus may also include a shared virtual address space register to provide translation for the first set of memory sections shared between processes and a process virtual address space register to provide translation for the second set of memory sections specific to the individual process. The translation for the second set of memory sections may be independent from the translation for the first set of memory sections.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: March 17, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Izzat El Hajj, Alexander Marshall Merritt, Gerd Zellweger, Dejan S. Milojicic, Paolo Faraboschi
  • Patent number: 10592146
    Abstract: A method of operating a data processing system 4 is disclosed that comprises producing data in the form of blocks of data, where each block of data represents a particular region of a data array, processing the data using a processing operation in which one or more output data values are each determined using data values from plural different lines of the data array, storing the processed data in a memory 21 of the data processing system, and reading the data from the memory 21 in the form of lines.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: March 17, 2020
    Assignee: Arm Limited
    Inventors: Sharjeel Saeed, Kushan Vijaykumar Vyas, Michal Karol Bogusz, Piotr Tadeusz Chrobak, Ozgur Ozkurt
  • Patent number: 10585621
    Abstract: A systolic array implemented in circuitry of an integrated circuit includes a processing element array including processing elements. The systolic array includes one or more feeder circuits communicatively coupled to the processing element array. Each of the one or more feeder circuits includes a first section configured to receive data stored in memory external to the integrated circuit, and a second section configured to send the received data to the processing element array, wherein data transferring from the memory to the processing element array is double buffered by the first section and the second section. The systolic array also includes one or more drain circuits communicatively coupled to the processing element array, including one or more memory buffers configured to store data output by the processing element array.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 10, 2020
    Assignee: Intel Corporation
    Inventors: Randy Huang, Yeong Tat Liew, Jason Gee Hock Ong
  • Patent number: 10585589
    Abstract: A data collation method in a storage array including reading first data from a first logical address without decompression, assigning, by a storage controller, a second logical address to the first data, storing the first data to the second logical address, establishing, by the storage controller, a mapping relationship between an address of a storage array and the second logical address, where the first logical address is mapped to a first physical address of a storage device, a length of the first physical address is equal to a length of first data, a length of the first logical address is equal to a length of second data, and the first data is compressed data of the second data, and receiving, by the storage controller, the first data from the storage device.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: March 10, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Mingchang Wei