Abstract: Provided are integrated circuits and methods for operating integrated circuits. An integrated circuit can include a plurality of memory banks and an execution engine including a set of execution components. Each execution component can be associated with a respective memory bank, and can read from and write to only the respective memory bank. The integrated circuit can further include a set of registers each associated with a respective memory bank from the plurality of memory banks. The integrated circuit can further be operable to load to or store from the set of registers in parallel, and load to or store from the set of registers serially. A parallel operation followed by a serial operation enables data to be moved from many memory banks into one memory bank. A serial operation followed by a parallel operation enables data to be moved from one memory bank into many memory banks.

Abstract: Techniques to update a trim parameter in non-volatile memory during either a manufacturing stage or a post-manufacturing stage are described. Trim parameters may be stored in a register located within the memory device that is inaccessible by a host device during a normal mode of operation. Post-manufacturing updates to trim parameters by the host device may be feasible by creating registers located within the memory device that are accessible to the host device to provide information regarding trim parameter setting updates. The memory device may read the information from the registers accessible to the host device to update trim parameters stored in the register inaccessible by the host device. In this manner, the host device may not have a direct access to the trim parameters but still be able to provide an update to the trim parameters by updating an entry of the registers accessible by the host device.

Abstract: An operating method of a semiconductor device and a memory system, each including a multi-connection port, includes: receiving connection information of a first device while connecting to the first device; updating information of a management table by using the connection information; and generating and transmitting a first packet including the connection information of the first device to a second device pre-connected to the memory system.

Abstract: An integrated-circuit buffer component includes a control-side data interface configurably coupled to first and second memory-side data interfaces via internal conductors, the first data interface having twice as many input/output (I/O) transceivers as the second data interface. In a first memory system configuration in which only the first data interface is coupled to a memory module, steering circuitry couples all the internal data conductors exclusively to the I/O transceivers of the first data interface. In a second memory system configuration in which the first and second data interfaces are coupled to respective memory modules, the steering circuitry couples a first half of the internal data conductors exclusively to the I/O transceivers of the second data interface while a second half of the internal data conductors remains exclusively coupled to half the I/O transceivers of the first data interface.

Abstract: Operations include storing and/or accessing data in tape volume containers. A system receives a request to access a tape block in a data storage tape. The system maps the requested tape block in the data storage tape to an object in a container. The system then retrieves data from the object in the container. The system generates, from the retrieved data, a data stream in tape archive format. The system transmits the data stream, in tape archive format, in response to the request to access the tape block in the data storage tape.

Abstract: Herein are data storage devices that transfer a reference to a data object during a storage operation. The data storage devices include a host controller configured to obtain a reference of an object stored in a shared memory system for writing to a storage media controlled by a drive controller. The host controller transfers the reference of the object in the memory system to the drive controller. The host controller also transfers a storage command to the drive controller to write the object to the storage media.

Abstract: Performing a calibration of a NAND flash memory block that is in an open state. An open state of the NAND flash memory block is detected, the NAND flash memory block comprising a plurality of memory pages, each of which comprising a plurality of memory cells. A group of pages of the NAND flash memory block being in an open state having comparable characteristics is identified. A calibration of read voltage values to pages of the group of identified pages is performed.

Abstract: A method of operating a data processing system 4 is disclosed that comprises producing data in the form of blocks of data, where each block of data represents a particular region of a data array, processing the data using a processing operation in which one or more output data values are each determined using data values from plural different lines of the data array, storing the processed data in a memory 21 of the data processing system, and reading the data from the memory 21 in the form of lines.

Abstract: According to examples, an apparatus may include a processor to address a physical memory having memory sections, in which a first set of memory sections may be shared between processes and a second set of memory sections may be specific to an individual process. The apparatus may also include a shared virtual address space register to provide translation for the first set of memory sections shared between processes and a process virtual address space register to provide translation for the second set of memory sections specific to the individual process. The translation for the second set of memory sections may be independent from the translation for the first set of memory sections.

Abstract: A systolic array implemented in circuitry of an integrated circuit includes a processing element array including processing elements. The systolic array includes one or more feeder circuits communicatively coupled to the processing element array. Each of the one or more feeder circuits includes a first section configured to receive data stored in memory external to the integrated circuit, and a second section configured to send the received data to the processing element array, wherein data transferring from the memory to the processing element array is double buffered by the first section and the second section. The systolic array also includes one or more drain circuits communicatively coupled to the processing element array, including one or more memory buffers configured to store data output by the processing element array.

Abstract: A data collation method in a storage array including reading first data from a first logical address without decompression, assigning, by a storage controller, a second logical address to the first data, storing the first data to the second logical address, establishing, by the storage controller, a mapping relationship between an address of a storage array and the second logical address, where the first logical address is mapped to a first physical address of a storage device, a length of the first physical address is equal to a length of first data, a length of the first logical address is equal to a length of second data, and the first data is compressed data of the second data, and receiving, by the storage controller, the first data from the storage device.

Abstract: Memory systems that can predict a physical address associated with a logical address, and methods for use therewith, are described herein. In one aspect, the memory system predicts a physical address for a logical address that follows a sequence of random logical addresses. The predicted physical address could be a physical location where the data for the logical address is predicted to be stored. In some cases, the host data can be returned without accessing a management table. The predicted physical address is not required to be the location of the data to be returned to the host for the logical address. In one aspect, the memory system predicts a physical address at which information is stored that may be used to ultimately provide the data for the logical address, such as a location in the management table.

Abstract: A memory controller for receiving a differential data strobe signal and an application processor having the memory controller are disclosed. The memory controller includes a strobe signal receiver configured to receive first and second strobe signals from a memory device as differential data strobe signal and output a first detection signal based on a level of each of the first and second strobe signals, a comparator configured to receive the second strobe signal and a reference voltage and compare a level of the second strobe signal with a level of the reference voltage to output a second detection signal, and a gate signal generator configured to generate a gate signal masking a portion of a period corresponding to the differential data strobe signal using the first detection signal and the second detection signal.

Abstract: The lookup of accesses (including snoops) to cache tag ways is serialized to perform one (or less than all) tag way access per clock (or even slower). Thus, for a N-way set associative cache, instead of performing lookup/comparison on the N tag ways in parallel, the lookups are performed one tag way a time. Way prediction is utilized to select an order to look in the N ways. This can include selecting which tag way will be looked in first. This helps to reduce the average number of cycles and lookups required.

Abstract: Technologies for dividing resources across partitions include a compute sled. The compute sled is to determine partitions among sockets of the compute sled. Each socket is associated with a corresponding processor. The compute sled is also to establish a separate memory space for each determined partition, obtain, from an application executed in one of the sockets, a request to access a logical memory address, identify the partition associated with the memory access request, determine a corresponding physical memory address as a function of the identified partition and the logical memory address, and access a memory of the compute sled at the determined physical memory address. Other embodiments are also described and claimed.

Abstract: The system can include a cache and cluster manager. The cache can store a plurality clusters, each of a plurality of clusters including a plurality of cache entries, each of the plurality of cache entries including a plurality of first metadata feature values. The cluster manager can assign a first cache entry corresponding to a data record located in memory to a first cluster based on determining a lowest distance. The lowest distance is determined by operations. The operations can include calculating a plurality of intra cluster feature means. The operations can include receiving a plurality of second metadata feature values of the first cache entry. The operations can include calculating a plurality of distances based on the plurality of intra cluster feature means and the plurality of second metadata feature values. The operations can include determining the first entry having a lowest distance of the plurality of distances.

Abstract: A method for performing a refresh operation on a memory cell efficiently is provided. A semiconductor device including a normal memory cell and a trigger memory cell that determines whether the refresh operation is performed or not is used. Specific data is written to the trigger memory cell, and the data is read from the trigger memory cell at predetermined timing. When the read data agrees with the written specific data, no special operation is performed. When the read data does not agree with the written specific data, a refresh operation is performed automatically.

Abstract: A method for adjusting over provisioning space and a flash device are provided. The flash device includes user storage space for storing user data and over provisioning space for garbage collection within the flash device. The flash device receives an operation instruction, and then performs an operation on user data stored in the user storage space according to the operation instruction. Further, the flash device identifies a changed size of user data after performing the operation. Based on the changed size of data, a target adjustment parameter is identified. Further, the flash device adjusts the capacity of the over provisioning space according to the target adjustment parameter. According to the method, the over provisioning ratio can be dynamically adjusted.

Abstract: A method of operating a data storage device includes: receiving a single wipe device initialization command from a host, and in response to the wipe device initialization command, executing a wipe device initialization operation that during a single time period initializes the entirety of a mapping table defining logical partitions dividing memory space provided by a physical region of the data storage device.

Abstract: The present disclosure is related to multidimensional contiguous memory allocation. Multidimensional contiguous memory allocation can include receiving an allocation request for an amount of memory that is contiguous in a multiple dimensions of the memory and determining whether the memory includes a region corresponding to the requested amount that is a candidate as being unallocated based on information indicating a maximum number of contiguous unallocated allocable portions of the memory. In response to determining that the memory includes the candidate region, the method can include determining whether the candidate region is unallocated based on a subset of information indicating whether each allocable portion of the memory is allocated. The subset of information corresponds to the candidate region only.