Patents Examined by Trang K Ta
  • Patent number: 9933974
    Abstract: A method of operating a data storage device includes: receiving a single wipe device initialization command from a host, and in response to the wipe device initialization command, executing a wipe device initialization operation that during a single time period initializes the entirety of a mapping table defining logical partitions dividing memory space provided by a physical region of the data storage device.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: April 3, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Il Su Han, Keun Soo Jo, Hee Chang Cho
  • Patent number: 9928210
    Abstract: The present disclosure provides for defragmenting deduplicated data, such as one or more backup image files, stored in a deduplicated data store. A defragmentation module can be implemented on a deduplication server to reduce fragmentation of backup images and improve processing time for restoring a backup image. A defragmentation module can be configured to defragment a backup image file by migrating portions of data of the backup image file that are stored in various containers at non-contiguous locations throughout deduplicated data store. A defragmentation module can contiguously write the portions to one or more containers, which are stored at one or more new locations in the deduplicated data store. A defragmentation module can be configured to evaluate whether portions of a backup image file meet criteria for defragmentation. A defragmentation module can also be configured to update location information about the portions that are migrated to the new container(s).
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: March 27, 2018
    Assignee: Veritas Technologies LLC
    Inventors: Xianbo Zhang, Benjamin Potvien, Thomas Hartnett, Weibao Wu, Satyajit Gorhe Parlikar
  • Patent number: 9927998
    Abstract: Systems and method for reading compressed data from non-volatile storage such as an SSD device are disclosed. A logical section, e.g. page, of data includes a plurality of data blocks that are compressed such that the lengths thereof are different. A header section of the page stores headers for the data blocks and storing a length for each data block. The header section may be a codeword encoding the headers according to an error correction scheme. To read out a data block a hardware decoder requests reading of the page and transfers the header section into a hardware decoder that decodes the headers to obtain an offset for a desired data block. Without instructing reading of the page, the offset is used by the hardware decoder to request transfer of the desired data block that is then decoded and returned to a requesting device.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: March 27, 2018
    Assignee: Tidal Systems, Inc.
    Inventors: Meng Kun Lee, Priyanka Thakore
  • Patent number: 9916096
    Abstract: For increasing data storage capacity using a processor device, increasing logical capacity of data storage having a multiplicity of storage units containing fixed partitioned segments by moving a selected number of the fixed partitioned segments in one or more storage units to a reserved storage unit.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: March 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yariv Bachar, Ron Edelstein, Alon Horowitz, Oded Sonin
  • Patent number: 9916253
    Abstract: A method for supporting a plurality of requests for access to a data cache memory (“cache”) is disclosed. The method comprises accessing a first set of requests to access the cache, wherein the cache comprises a plurality of blocks. Further, responsive to the first set of requests to access the cache, the method comprises accessing a tag memory that maintains a plurality of copies of tags for each entry in the cache and identifying tags that correspond to individual requests of the first set. The method also comprises performing arbitration in a same clock cycle as the accessing and identifying of tags, wherein the arbitration comprises: (a) identifying a second set of requests to access the cache from the first set, wherein the second set accesses a same block within the cache; and (b) selecting each request from the second set to receive data from the same block.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: March 13, 2018
    Assignee: Intel Corporation
    Inventors: Karthikeyan Avudaiyappan, Sourabh Alurkar
  • Patent number: 9886313
    Abstract: A system includes a first node including a first processor and a first memory, and a second node including a second processor and a second memory. A worker thread of the first processor calls an allocation API to allocate a portion of the first memory, and calls a first allocator of a first memory manager associated with the first node to allocate a specified size of the first memory. The first memory manager calls an operating system function to reserve a memory segment of the specified size, sets a first Non-Uniform Memory Access policy of the first node to preferred, binds the reserved memory segment to the first node, adds the memory segment to a global freelist, and returns an address pointer of the reserved memory segment to the worker thread.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: February 6, 2018
    Assignee: SAP SE
    Inventors: Mehul Wagle, Daniel Booss, Ivan Schreter