Patents Examined by Tri Hoang
  • Non-volatile memory programming
    Patent number: 9202586
    Abstract: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying a signal to a line associated with a memory cell, the signal being generated based on digital information. The method can also include, while the signal is applied to the line, determining whether a state of the memory cell is near a target state when the digital information has a first value, and determining whether the state of the memory cell has reached the target state when the digital information has a second value. Other embodiments including additional memory devices and methods are described.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: December 1, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Giovanni Santin, Michele Incarnati
  • Resistance-based memory cells with multiple source lines
    Patent number: 9196339
    Abstract: In a particular embodiment, a device includes a resistance-based memory cell having multiple source lines and multiple access transistors. A coupling configuration of the multiple access transistors to multiple source lines encodes a data value.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 24, 2015
    Assignee: QUALCOMM Incorporated
    Inventor: Xiangyu Dong
  • Read distribution management for phase change memory
    Patent number: 9196359
    Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: November 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Ferdinando Bedeschi, Roberto Gastaldi
  • Memory having a voltage switch circuit with one bias voltage changed in each state of conditioning
    Patent number: 9190415
    Abstract: A voltage switch circuit includes four transistors. The four transistors may be transistors used to build logic gates. The operation of the voltage switch circuit may include precharging the output terminal of the voltage switch circuit, conditioning of the voltage switch circuit and boosting the voltage of the output terminal.
    Type: Grant
    Filed: June 29, 2014
    Date of Patent: November 17, 2015
    Assignee: eMemory Technology Inc.
    Inventor: Chen-Hao Po
  • Voltage regulator, voltage regulating system, memory chip, and memory device
    Patent number: 9188999
    Abstract: A voltage regulator comprises a power source terminal configured to supply a power source voltage; an output terminal configured to output a load current; a first transistor which is connected between the power source terminal and the output terminal, is enabled by a signal applied from an amplifier in a first mode to generate a first current, and outputs the first current to the output terminal; and a second transistor which is connected between the power source terminal and the output terminal, is enabled by a signal applied from the amplifier in a second mode to generate a second current different from the first current, and outputs the second current to the output terminal, wherein the first transistor is enabled in the second mode, and the second transistor is disabled in the first mode.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: November 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-Sung Lee, Dong-Hun Heo
  • Thermal treatment of flash memories
    Patent number: 9183941
    Abstract: A memory controller can provide current to a heater in a flash memory to reduce cycling induced errors. If necessary, after heating, the memory may be refreshed. In non-battery powered systems, data may be removed from the memory prior to heating and restored to the memory after heating.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: November 10, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Gian Pietro Vanalli, Stefano Corno, Giovanni Campardo, Angelo Visconti, Silvia Beltrami, Alexey Petrushin
  • Circuits and methods of a self-timed high speed SRAM
    Patent number: 9183897
    Abstract: Circuits and methods for precisely self-timed SRAM memory are disclosed to track the wordline and/or bitline/bitline bar (BL/BLB) propagation delays. At least one reference cell can be placed near the far end of a driver to drive a selected wordline or a reference wordline. When a wordline and/or a reference wordline is turned on, the reference cell can be selected not earlier than any selected SRAM cells and can activate a reference bitline (RBL) not later than any selected SRAM cells activating the BL or BLB. The activation of the RBL can be used to trigger at least one sense amplifier. The RBL can also be used to de-select wordline or reference wordline after the sense amplifier operation is complete to save power.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 10, 2015
    Inventor: Shine C. Chung
  • Memory and sense parameter determination methods
    Patent number: 9171633
    Abstract: Memory devices and methods for operating a memory include filtering a histogram of sensed data of the memory, and adjusting a parameter used to sense the memory using the filtered histogram. Filtering can be accomplished by averaging or summing, and may include weighting the sums or averages.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: October 27, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Zhenlei Shen, William H. Radke
  • High-reliability high-speed memristor
    Patent number: 9165645
    Abstract: A memristor has a first electrode, a second electrode parallel to the first electrode, and a switching layer disposing between the first and second electrodes. The switching layer contains a conduction channel and a reservoir zone. The conduction channel has a Fermi glass material with a variable concentration of mobile ions. The reservoir zone is laterally disposed relative to the conduction channel, and functions as a source/sink of mobile ions for the conduction channel. In the switching operation, under the cooperative driving force of both electric field and thermal effects, the mobile ions are moved into or out of the laterally disposed reservoir zone to vary the concentration of the mobile ions in the conduction channel to change the conductivity of the Fermi glass material.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: October 20, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Feng Miao, Jianhua Yang, John Paul Strachan, Wei Yi, Gilberto Medeiros Ribeiro, R Stanley Williams
  • Memory chip and semiconductor package including the same
    Patent number: 9159387
    Abstract: A memory chip includes a data processing block suitable for serial-parallel converting data inputted and for parallel-serial converting data to be outputted, a write data transmitting unit suitable for transmitting the data serial-parallel converted by the data processing block to a write data interlayer channel, a write data receiving unit suitable for receiving data from the write data interlayer channel, the data to be written to a core area, a read data receiving unit suitable for receiving data from a read data interlayer channel, the data to be parallel-serial converted by the data processing block, and a read data transmitting unit suitable for transmitting data read from the core area to the read data interlayer channel.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: October 13, 2015
    Assignee: SK Hynix Inc.
    Inventor: Sang-Jin Byeon
  • Tracking read accesses to regions of non-volatile memory
    Patent number: 9141534
    Abstract: A data storage device includes a memory and a controller and may perform a method that includes updating, in the controller, a value of a particular counter of a set of counters in response to a read access to a particular region of the non-volatile memory that is tracked by the particular counter. Read accesses to a first region of the non-volatile memory are tracked by a first counter of the set of counters and read accesses to a second region of the non-volatile memory are tracked by a second counter of the set of counters. The method includes, in response to the value of the particular counter indicating that a count of read accesses to the particular region equals or exceeds a first threshold, initiating a remedial action to the particular region of the non-volatile memory.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: September 22, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Manuel Antonio D'Abreu, Stephen Skala
  • Semiconductor device having level shifter
    Patent number: 9136844
    Abstract: Disclosed herein is a semiconductor device that includes: an internal voltage generator configured to produce an internal voltage in a first mode and stop producing the internal voltage in a second mode; a level shifter configured to receive the internal voltage, a first voltage and a first signal, in order to convert the first signal from a voltage level of internal voltage to a voltage level of the first voltage and output the first signal with the voltage level of the first voltage; and a logic circuit configured to produce the first signal, the logic circuit being supplied with the internal voltage in the first mode and supplied with the first voltage in the second mode.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: September 15, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Kiyohiro Furutani
  • Tracking erase pulses for non-volatile memory
    Patent number: 9129689
    Abstract: A data storage device includes a memory and a controller and may perform a method that includes comparing, in the controller, a count of erase pulses to an erase pulse threshold. The count of erase pulses corresponds to a particular region of the non-volatile memory. The method includes, in response to the count of erase pulse satisfying the erase pulse threshold, initiating a remedial action with respect to the particular region of the non-volatile memory.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: September 8, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Manuel Antonio D'Abreu, Dimitris Pantelakis, Stephen Skala
  • Memory system and method using stacked memory device dice
    Patent number: 9123394
    Abstract: A method and apparatus for organizing memory for a computer system including a plurality of memory devices, connected to a logic device, particularly a memory system having a plurality of stacked memory dice connected to a logic die, with the logic device having capability to analyze and compensate for differing delays to the stacked devices stacking multiple dice divided into partitions serviced by multiple buses connected to a logic die, to increase throughput between the devices and logic device allowing large scale integration of memory with self-healing capability.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: September 1, 2015
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Byoung Jin Choi
  • Tracking erase operations to regions of non-volatile memory
    Patent number: 9117533
    Abstract: A data storage device includes a memory and a controller and may perform a method that includes updating, in the controller, a value of a particular counter of a set of counters in response to an erase operation to a particular region of the non-volatile memory that is tracked by the particular counter. The method includes, in response to the value of the particular counter indicating that a count of erase operations to the particular region satisfies a first threshold, initiating a remedial action to the particular region of the non-volatile memory.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: August 25, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Manuel Antonio D'Abreu, Dimitris Pantelakis, Stephen Skala
  • SRAM bit cell with reduced bit line pre-charge voltage
    Patent number: 9111638
    Abstract: An SRAM bit cell comprises a first inverter including a PMOS transistor and an NMOS transistor, and a second inverter including a PMOS transistor and an NMOS transistor. The first and second inverters are cross-coupled to each other. A plurality of pass transistors couple the inverters to bit lines. Approximately one-half of a supply voltage is provided to the bit lines during pre-charge operations.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: August 18, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: James D. Burnett, Perry H. Pelley
  • Methods of driving a memory
    Patent number: 9105339
    Abstract: Methods of driving a memory include erasing a plurality of memory cells of a memory device, testing whether the memory cells have been erased, and programming the memory cells without erasing the memory cells again if more than a predetermined percentage of the memory cells, but less than all of the memory cells, were successfully erased.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: August 11, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moshe Twitto, Jun-Jin Kong
  • Resistance change type memory
    Patent number: 9093148
    Abstract: According to one embodiment, a resistance change type memory includes a first and a second bit lines, a memory cell connected between the first and second bit lines and including a variable resistance element as a memory element and a first select element including a first control terminal connected to a word line, and an auxiliary circuit connected to the first bit line and including a second select element including a second control terminal connected to a control line. When data is read from the memory cell, a first current in a read current supplied to the first bit line is supplied to the memory element and the first select element, and a second current in the read current is supplied to the second select element.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: July 28, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kosuke Hatsuda
  • Sub word line driver and semiconductor integrated circuit device
    Patent number: 9082467
    Abstract: A sub word line driver and a semiconductor integrated circuit device having the same are provided. The semiconductor integrated circuit device includes adjacent four sub word line drivers configured to drive four sub word lines in response to signals of four main word lines, wherein first and second sub word line drivers of adjacent sub word line drivers share one keeper transistor with each other, and third and fourth sub word line drivers of the adjacent sub word line drivers share one keeper transistor with each other.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: July 14, 2015
    Assignee: SK Hynix Inc.
    Inventors: Tae Sik Yun, Dong Hwee Kim
  • Semiconductor device
    Patent number: 9082642
    Abstract: Disclosed is a semiconductor device, including: an active region defined in a shape extended in at least four different directions in a semiconductor substrate; and gates of first to fourth transistors formed on extended portions of the active region, respectively, in which the first to fourth transistors share one junction area.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: July 14, 2015
    Assignee: SK Hynix Inc.
    Inventors: Hyun Sub Kim, Jung Won Park