Abstract: Data is encoded to maximize subsequent recovery of lost or damaged compression constants of encoded data. In one embodiment, a compression constant is used to define a randomization pattern and the data is randomized using the randomization pattern. In one embodiment, a bit reallocation process and code reallocation process are performed on the data to randomize the data.

Abstract: A test link protocol which continuously monitors each link in a network to ensure that the link is correctly transmitting data. Each switch, or torus has at least one of two functional components: Send Test and Receive Test. The Send Test component monitors control codes at a torus link output. The Receive Test component monitors control codes at a torus link input. After a predetermined interval, the Send Test component makes a request to send a test.sub.-- link control code. The torus sends the test.sub.-- link code to the neighboring torus, where it is removed from the data stream and sent to that torus' Receive Test. The Receive Test then generates a response message and makes a request to send that message back to the originating torus. After receiving the message, the Send Test analyzes the message to determine whether the network link is working correctly. An error is also declared if the Send Test does not receive a reply within a predetermined interval.

Abstract: A single integrated circuit transceiver on a single substrate which can perform synchronous data transmissions that comply with CCITT recommendation V.35 in either the DTE or DCE mode is provided. The same chip can be configured to provide a diagnostics loopback, with the loopback being performed one way for a DTE mode and another way for a DCE mode. The invention provides a simple, elegant solution which minimizes the number of gates and maximizes the benefits.

Abstract: A fault tolerant processing system including a prediction RAM employs a Lock Step Compare routine. The method developed allows the processing system to recover from single event upsets. In initialization, the branch prediction RAM is set to a known value. An engineering balance is achieved by adding logic to detect a branch RAM error and incurring the delay of re-initializing the entire RAM only when a RAM error has been detected.

Abstract: Fault tolerant systems allow continuous service during the occurrence of a hardware failure. To provide such service, usually dual copies of data are stored in case of a hardware failure affecting the original copy. This dual copying causes the system an overall performance degradation. The present invention discloses a device and method for performing parallel fetch and store commands, allowing multiple copying of data into storage without affecting the performance of the system. In one embodiment of the invention, a method is described utilizing a multiprocessor system having two system controllers (SCs) and a plurality of requestors defined as a plurality of central processors (CPs) and input-output (I/O) processors. Asymmetric structure is accomodated. Single and dual requests can be intermixed. Each requestor has access to both system controllers, allowing either controller to process a requestor issued command.

Abstract: A self-diagnostic device for checking the performance of memory matrix in semiconductor devices is presented. The device is applicable particularly to those IC testers having high bit and high capacity memories. The device is capable of performing march and checker tasks simultaneously. The program data contained in a CPU 1 are written into the memory matrix 5 by way of the data generation circuit 2 and the address generation circuit 3. The test data are entered into a comparator 4 at the timing governed by the clock generation circuit 6, and are compared with the expected data from the data generation circuit 2. When there is a non-coincidence, a defect signal is generated from a flip-flop (FF) circuit 9. In the present device, the conventional division circuits are replaced by two FF circuits 8, 9, and two EOR-gates 11, 12 and associated components to provide simplicity in circuit configuration and efficient operation while retaining the advantages offered by the conventional march- and checker-modes.

Abstract: A library of performance monitor recordings is maintained according to pathologies. The library is indexed to provide a facility to diagnosis poorly performing data processing systems, by capturing performance statistics and comparing these statistics against known problematic statistics. Remote diagnosis can easily be provided by a user capturing a performance session, saving to a file, and transferring the file to a central facility for comparison against its pathological libraries.

Abstract: A program debugging system has a core unit that includes a plurality of debugger memory areas, each uniquely associated with a corresponding one of a plurality of debuggers. The core unit responds to an exception condition by selecting one debugger from the plurality of debuggers, selection being made by determining which one of the debuggers is associated with the program exception. Then, computer state information and debugger state information are stored into a selected one of the debugger memory areas that is exclusively associated with the selected debugger, and the selected debugger is activated. A new debugger may register with the core unit, so that the new debugger is added to the plurality of debuggers. The activated debugger may send a debugging command to the core unit, which responds by updating debugger state information based on the received debugging command, and storing the updated debugger state information into the selected debugger memory area.

Abstract: A computer communications system has a controller for controlling a master with a circuit timer, the circuit timer is capable of aggregating data produced during a circuit timer interval into a single master message, and the data is produced by a plurality of users, where each user is capable of establishing a plurality of sessions. There is a communication pathway, responsive to expiration of the circuit timer interval, for sending the aggregated data to a slave. Also there is a acknowledgement circuit for the slave to send an acknowledge message to the master upon expiration of a delay ACK time interval, the delay ACK time interval is greater than the circuit timer interval, and the circuit timer is capable of initiating sending of a plurality of master messages during one delay ACK time interval.

Abstract: A transmission circuit transmits a normal cell data and an idle cell data via a communication line. The idle cell data is transmitted to fill time slots in the communication line at which there is no normal data to be transmitted, each of the normal cell data and idle cell data including first data, second data and third data. The first, second and third data of the normal cell data respectively indicate a destination, an error correcting code of the first data and desired information. The first and second data of the idle cell data have predetermined bit patterns and the third data of the idle cell data may have any arbitrary bit pattern.

Abstract: There are provided a data transmitter for sequentially transmitting data to which error correcting codes are added, and a data receiver for returning a retransmission request signal if the received data has errors which cannot be corrected. The data transmitter does not confirm that the retransmission request signal related to the transmitted data is received and data are consecutively transmitted from a FIFO memory in a pipeline fashion while holding the transmitted data in a data latch. The data receiver sequentially stores the received data in the FIFO memory on a receiving end in a pipeline fashion. In the case where the retransmission request signal is transmitted from the data receiver, the data transmitter immediately transmits retransmission data which has been prepared in the data latch.

Abstract: In a system for testing an instruction queue circuit connected to an external memory via a bus controller provided in a processor having a microprogram control unit, an operation unit connected to the microprogram control unit and connected, via an internal bus, to the instruction queue circuit, the instruction queue circuit-including a plurality of queue buffers, a writing unit writes internal bus information transferred via the internal bus into the instruction queue circuit in response to a first instruction generated by the microprogram control unit. The internal bus information is contained in the first instruction. A reading unit reads the internal bus information from the instruction queue circuit in response to a second instruction generated by the microprogram control unit. A gate circuit outputs the internal bus information to the internal bus in response to a third instruction generated by the microprogram control circuit. The internal bus information is used to test the instruction queue circuit.

Abstract: In control using a patch correctable microcomputer, the patch correction can have no effect on the timing of the control operation of the micro computer. Call instructions CALL 1, CALL 2 . . . for shifting, in synchronism with the operation of the microcomputer, over to a patch correction program in a RAM, are intermittently inserted into a control program stored in a ROM. A reciprocal number of invalid instructions NOP are put after this patch correction program in accordance with the length of the patch correction program. After a patch correction program has been carried out, the program in the ROM is returned to after a passage of time set according to the number of invalid instructions, so that the time for execution of the program in the RAM which is based on the microcomputer call instruction can be made constant irrespective of the length of time of the patch correction program, and will therefore have no effect on the timing for carrying out the program in the ROM.

Abstract: An integrated circuit for encoding digital data in the recording mode and decoding digital data in the reproduction mode using an error correction product code can be used in combination with a standard frame memory when use is made of a high-frequency system clock. An error correction strategy suitable for digital video is implemented in the circuit.

Abstract: A dynamic random access memory device internally carries out inspection sequences in a diagnostic mode of operation, and an instruction circuit incorporated therein discriminates a Write-CAS-Before-RAS entry cycle for simultaneously supplying test enable signals indicative of inspection sequences to internal test circuits, wherein the instruction circuit firstly decodes a multi-bit instruction signal and repeatedly produces a latch control signal for sequentially storing the decoded signal so that a plurality of test enable signal are simultaneously supplied to the test circuits.

Abstract: An improved apparatus and method for isolating faults in a complex communications network such as a collision-detection network. A wrap plug connected to a communications adapter of a computer system simulates multiple functions of the network environment, rather than a single, hardwired function. A method performs a comprehensive yet convenient diagnostic test of multiple functions of the adapter while a terminal is disconnected from the network.

Abstract: The invention relates to a method and apparatus for checking the integrity of a message such as a program and/or data against an original message supposed to correspond to it.By using an algorithm (A) on at least part of the original message, at least one signature (S1, S2, . . . Sm) of this part is calculated and memorized in a memory area (10) of a portable object (1) which also has processing circuits (11) able to implement algorithm (A). In order to check the integrity of a message, at least one signature of a message part is calculated by the processing circuits (11) of the portable object by implementing the algorithm (A) and is compared to an original message signature supposed to correspond, and memorized in memory area (10).

Abstract: An information processing apparatus includes a plurality of processors, a memory unit, a plurality of address conversion tables, an address conversion table managing unit, an address conversion table control unit, a processor managing unit, and an abnormality processing unit. The processors perform arithmetic operations for information processing. The memory unit is accessed commonly by the processors. The address conversion tables convert a logic address into a physical address. The address conversion table managing unit has directories for managing the address conversion tables in accordance with contents of the logic address and Nos. of processors accessible to the address conversion tables. The address conversion table control unit updates the address conversion table managing unit to update contents of the address conversion tables. The processor managing unit checks whether each processor is operable. The abnormality processing unit performs processing for deleting a specific processor No.

Abstract: In a data packet communications network capable of transmitting a digitally coded data packet message including an error-check code from a source node to a destination node over a selected transmission link which includes at least one intermediate node operative to intentionally alter a portion of a message to form an altered message which is ultimately routed to the destination node, a method of recomputing at the intermediate node a new error-check code for the altered message with a predetermined number of computational operations, i.e. computational time, independent of the length of the message, while preserving the integrity of the initially computed error-check code of the message.

Abstract: A data storage system is described which provides for fault tolerance during execution of a media maintenance program on a selected track of nonvolatile data storage. Checkpoint data for the media maintenance program is stored in nonvolatile storage prior to writing control information on the selected track during the execution of the media maintenance program. The checkpoint data includes an address in the media maintenance program for resuming execution in the event that the media maintenance process is aborted. The checkpoint data is read from the nonvolatile storage area after media maintenance has been aborted by a fault, typically after power has been reapplied to the system. The execution environment for the media maintenance program is restored by storing data in the RAM of the controller which duplicates the control data needed by the particular segment of the media maintenance program which will be restarted.