Abstract: An optical disk apparatus, in which the data supplied from a host computer is recorded on an optical disk by storing the data into a data buffer memory via an interface, by outputting the data to a recording-reproducing section, and by accessing the data buffer memory in time-sharing fashion. The data is reproduced from the disk by performing, in time-sharing fashion, the inputting of the data from the recording-reproducing section into the data buffer memory and the outputting of the data to the host computer via the interface. Since only one data buffer memory is used, the apparatus need not have a large circuit board and and can be manufactured at low cost.

Abstract: An array disk subsystem including a command selector for separating a signal from a host into a data item and a command, a data dividing unit for subdividing the data item, an ECC generator for producing an ECC for each of the obtained subdata items, a group of data disks for respectively storing thereon the subdata items and the ECCs, a command interpreting unit for interpreting the command, an I/O counter for counting I/O commands in the command, a backup processor for requesting a backup command based on count information of the I/O counter, and a backup unit responsive to the backup command for sequentially reading the subdata items and the ECCs from the data disks to record therein the subdata items and the ECCs.

Abstract: The invention provides greater error correction capability in an error correction encoding/decoding system of a digital mobile telephone or so forth. In a viterbi decoding system at a receiver side, a branch metric is calculated and stored without selecting a path with respect to a plurality of branches corresponding to a parameter having a correlation between frames. Also, by utilizing a separately stored parameter value in a previous frame, a transition probability of the parameter value in the current frame is obtained, a metric value of a path is converted and added to an accumulated path metric value up to the previous branch, a comparison of the metric values at various states is performed to select the path having higher likelihood to perform decoding by maximum likelihood decoding.

Abstract: A method and apparatus for the generation of a signal flag in response to illegal channel code patterns from an information channel, the signal flag may typically be used as an erasure flag by a subsequent error correction decoder. This erasure flag, being indicative of a data error position which can then be fed into a utilization circuit such as an error correction logic for performance improvement. In particular, a Miller-squared channel code format decoder in accordance with the present invention can easily and inexpensively provide error position information thereby enhancing error correction power, such as that of a Reed-Solomon error correction code.

Abstract: In accordance of the invention, the Erasable and Programmable Logic Device comprising a test circuit of the input architectures is provided.The test circuit comprises an extra test line 39, a plurality of EPROM transistors 34 having respectively the drain thereof connected to the extra test line and the gate thereof connected to a true input line provided from said one input architecture, sensing means 36 connected to the extra test line for sensing the state of the extra test line, and a buffer circuit 37 connected to the sensing means.

Abstract: In an integrated circuit comprising discrete circuit modules, dedicated test signals for the individual circuit modules are multiplexed with operational signals to the external pins of the integrated circuit. When not in a test mode, the external pins of the chip are coupled to the normal operational signals. When a test mode is commanded, certain external pins are coupled to test signals that are not otherwise available off-chip in accordance with the contents of a test register.

Abstract: A mode control circuit is disclosed which generates a mode control signal in response to an illegal state detected as a combination of inputs and outputs. An illegal state is forced by the application of a fixed voltage to an output pin. The mode control signal is used to switch input-output signals of a megacell internal to an application specific integrated circuit to the output pins of the package so that testing of the megacell is facilitated.

Abstract: A debug program is decoded in a command decoder to generate a debug start signal. Then, a signal processing operation is halted and a state of an internal circuit is latched and read to be supplied to an external circuit. When the reading of the state starts, a signal-processing continuation signal is generated, so that the signal processing operation is restored to be continued. Therefore, the debug program can be inserted to a program memory at plural addresses without braking the signal processing operation.

Abstract: A timer unit that permits individual timer registers to be taken offline from the timer complex. A single register is taken offline instead of checkstopping the entire computer system due to a damaged timer, for example, thereby reducing system outages and thus providing increased availability of the system.

Abstract: A method and an apparatus are applied to the seismic data received by receivers (Ri) distributed in the field and collected by acquisition boxes (Bi), in order to be transmitted to a central control and recording station (P), for example through hertzian channels. Digital words by adding to each N1-bit digitized signal sample, in each acquisition box, a n-bit coding suffix sufficient for detecting and correcting any transmission-related error. In order to eliminate the effect of long interferences, the method also comprises arranging the words in blocks, interleaving the words of each block at the time of the transmission, and forming digital symbols. A complementary sequence for reverse interlacing, deblocking and correcting possible errors brings the digital samples back to the original state thereof.

Abstract: A semiconductor integrated circuit includes a plurality of input buffers, a plurality of high level signal abnormality detection circuits each connected to an output of a corresponding one of the input buffers, and a plurality of low level signal abnormality detection circuits each connected to an output of a corresponding one of the input buffers. A first concentrating circuit is connected to all the high level signal abnormality detection circuits so as to output a first abnormal signal when at least one of the high level signal abnormality detection circuits detects an abnormal high level signal, and a second concentrating circuit is connected to all the low level signal abnormality detection circuits so as to output a second abnormal signal when at least one of the low level signal abnormality detection circuits detects an abnormal low level signal.

Abstract: A portable computer including a CPU, a detachable hard disk pack which is connectable to a system bus of the portable computer, and a hard disk pack replacement detector which detects, in a power-Off state, a detachment of the disk pack and sets a signal in a status register indicating the detachment of the disk pack. In response to a power-ON state, the CPU reads the status register to determine whether the disk pack had been detached during the power-OFF state and, if so, disables a resume flag so that operation does not resume at the operating state of the portable computer which existed immediately preceding the power-OFF state.

Abstract: A method for evaluating application software used with a computer system having a graphic user interface. The method is implemented as a computer program that runs simultaneously with the application software. The program continually checks a system-provided event record to determine if a user-initiated event has occurred. If so, the program relates the event to an on-screen object of the graphic user interface and to the time at which it occurred. Events and objects and their attributes are associated with identifiers so that the invention can be programmed to select only certain event data. The program outputs an event capture log, which may be used for subsequent analysis.

Abstract: An improved solid state storage device (SSD) with memory organized into a plurality of groups, each group including a plurality of ranks, and each rank having at least two banks sharing a bidirectional data bus. A matrix reorder circuit is used to distribute data across individual memory components in a way that prevents multibit uncorrectable or undetectable errors due to the failure of a single memory component. The matrix reorder circuit is used for both reading and writing data, and operates on a stream of pipelined data of arbitrary length.

Abstract: Digital data is processed by quantizing the data to produce samples, each with a most significant bits and least significant bits with the least significant bits representing reliabilities, generating a parities from the most significant bits of the samples, generating weight functions corresponding to the parities on the basis of the number of times a reliability measure occurs, and producing a corrected stream of data with the weight functions and the corresponding parities.

Abstract: A fault tolerant three port communications module has two control ports for receiving commands from two computers, and a communications port for transferring data over a communications channel in response to the commands. Each control port includes a select line which carries a select signal with true and false states, mode lines which carry codes that represent the commands, and a write line which carries a respective pulse in sync with each of the codes. The select line, mode lines, and write line of each control port are coupled in the module to a respective inter-processor command decoder having a lead stage and a trail stage.

Abstract: A method for handling data in a plurality of data storage disks having user data sectors and corresponding parity sectors, the method being used when the disks are being operated in a degraded mode wherein data in sectors of an inoperative user data disk are reconstructed from data in the corresponding sectors of the other user data disks and the corresponding parity entry. The reconstructed user data in a user data sector of the inoperative disk is written into the corresponding parity sector in place of the parity entry therein, before any new data is written into the corresponding sector of an operative disk. Information identifying the inoperative disk is written into a specified identification region of the parity disk to indicate that such operation has occurred. The new data is then written into the corresponding sector of the operative disk.

Abstract: A method in a computer system for monitoring time intervals during which external interrupts are inhibited within the computer system in a selected program being run on the computer system. The method and apparatus of the present invention includes identifying a first plurality of instructions, capable of blocking external interrupts and identifying a second plurality of instructions, capable of unblocking external interrupts. After identifying these instructions, a unique benign fault is inserted proximate to selected ones of the first plurality of instructions and selected ones of the second plurality of instructions to produce a special version program. The special version program is then run in the computer system. Faults which occur during the running of the special version program and associated external interrupt-blocking times are monitored.

Abstract: Apparatus and method of a data cache which provides for the handling of errors during data copy-back from a data cache write buffer to external memory in a processing system including a processor. When data requested by the processor at an addressed storage location of the data cache is data which is valid, modified, and other than the data requested by the processor, the data is first transferred to the data cache write buffer and then written back to external memory after the requested data is fetched from a memory bus. If an error occurs during the write back of the data from the write buffer to external memory, the data is transferred from the write buffer to the storage location of the data cache originally addressed by the processor before the memory bus is released.

Abstract: An error correcting code and apparatus are used in conjunction with a main memory in which a data word is stored in a plurality of circuits each of which produces multiple outputs. A minimum number of check bits are stored together with the data word for detecting and correcting single bit errors and detecting the existence of multi-bit errors. A parity bit for the entire data word is also stored. For a 32-bit data word, at least 3 bits of the data word are stored in each of 10 memory circuits. Seven check bits and one parity bit are also stored in the 10 memory circuits wherein no more than one of the check bits or parity bit is stored in any one memory circuit. Upon reading the data word from the memory a set of verify check bits and a verify parity bit are generated and compared to the stored check bits and stored parity bit to produce a check bit syndrome and a parity bit syndrome.