Abstract: A memory cell array including at least one memory cell, an address storage section containing address information, an address judging circuit for judging whether an input address matches the address information in the address storage section and outputting a result of the judgment, and a write or erase voltage generation circuit for generating a write or erase voltage to be applied to the memory cell are provided. The write or erase voltage generation circuit receives the output result from the address judging circuit and changes a write or erase voltage.

Abstract: A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell comprising a silicon, germanium or silicon-germanium diode, doping the diode with at least one of nitrogen or carbon, and forming a second electrode over the at least one nonvolatile memory cell.

Abstract: Systems, methods, and devices are disclosed, including an electronic device that includes a first data location, a quantizing circuit, and a reference current source, all coupled to an electrical conductor. The reference current source may include a current mirror with a side coupled to the electrical conductor and a second data location coupled to another side of the current mirror.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.

Abstract: A method for determining whether to store binary information in a fast way or a slow way of a cache is disclosed. The method includes receiving a block of binary information to be stored in a cache memory having a plurality of ways. The plurality of ways includes a first subset of ways and a second subset of ways, wherein a cache access by a first execution core from one of the first subset of ways has a lower latency time than a cache access from one of the second subset of ways. The method further includes determining, based on a predetermined access latency and one or more parameters associated with the block of binary information, whether to store the block of binary information into one of the first set of ways or one of the second set of ways.

Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

Abstract: A device and a method for automatically turning over a disc relate to a guide rod provided with a movable member. The movable member is assembled to a rotating member via a pivot member in such a manner that the movable member can axially move along and radially rotate around the guide rod. The pivot member is disposed between the movable member and the rotating member and powered to rotate. The rotating member is provided with a disc-carrying device in a direction of its rotation around the pivot member for taking the disc. The pivot member drives the disc to rotate via the rotating member, so as to turn over the disc, so that the rotating member makes the disc slide down into the tray in an inclined manner.

Abstract: A multi-chip package memory includes an interface chip generating at least one reference signal defined in relation to a reference process variation, and a stacked plurality of memory chips electrically connected to the interface chip via a vertical connection path and receiving the reference clock signal via the vertical connection path, wherein each one of the stacked plurality of memory chips is characterized by a process variation and actively compensates for said process variation in relation to the reference signal.

Abstract: A nonvolatile memory device, using a resistance material, includes a memory cell array having nonvolatile memory cells arranged in a matrix, multiple bit lines, a column selection circuit and column drivers. The bit lines are coupled to columns of the nonvolatile memory cells in the memory cell array. The column selection circuit selects at least one bit line in response to column selection signals. Each column driver supplies a column selection signal, and includes a first charge unit that charges an output port of the column driver to a first voltage level in response to a first charge signal, a second charge unit that charges the output port of the column driver to a second voltage level from the first voltage level in response to a second charge signal, and a current controller that controls a current path from the second charge unit to the first charge unit.

Abstract: A semiconductor memory device having read and write operations includes a discrimination signal generating unit for generating a discrimination signal during the write operation; and a selective delay unit for receiving and selectively delaying a command-group signal in response to the discrimination signal.

Abstract: A semiconductor memory device includes a memory block having first and second word lines extending in a first direction and bit lines extending in a perpendicular second direction; a first driver region at a side of the memory block in the first direction driving the first word lines; a second driver region at another side of the memory block in the first direction driving the second word lines; a sensing region at a side of the memory block in the second direction controlling the bit lines responsive to signals from drive lines; a first conjunction region at an intersection of the first driver and sensing regions including a first driver driving the drive lines responsive to signals from control lines; and a second conjunction region at an intersection of the second driver and sensing regions, including a second driver driving the drive lines responsive to signals from the control lines.

Abstract: A core voltage discharger is capable of adjusting an amount of a current discharged according to temperature. The discharger for decreasing a level of a predetermined voltage receives temperature information from an on die thermal sensor and discharges a different amount of current in response to the temperature information.

Abstract: A memory is so formed that, in a first block and a second block each including a prescribed number of the bit lines arranged therein, positions of the bit lines simultaneously selected in the first and second blocks with reference to ends of the first and second blocks respectively are different from each other.

Abstract: A plurality of memory blocks includes real memory cells and redundancy memory cells, are accessed independently during a normal operation mode, and are accessed simultaneously during a test mode in order for common data to be written to the plurality of memory blocks. A block control unit selects the plurality of memory blocks irrespective of a block address signal in order to execute a compression test. During the test mode, a redundancy access unit simultaneously accesses the redundancy memory cells of the plurality of memory blocks when a forced redundancy signal supplied to a block address terminal indicates first level. Therefore, the redundancy memory cells of the plurality of memory blocks may simultaneously access and test without providing any special terminal. As a result, before a defect is relieved, an operation test of the redundancy memory cells may efficiently execute, which may shorten the test time.

Abstract: A memory is secured against an error injection during the reading of a datum. The memory includes: means for reading a reference datum in the memory during a phase of reading a datum stored in the memory; means for comparing the reference datum read with an expected value; and means for generating an error signal if the datum read is different from the expected value. Application is provided particularly but not exclusively to the protection of memories integrated into smart cards.

Abstract: Memory devices and methods for operating such devices are described herein. A method as described herein includes applying a fixed sequence of voltage pulses across the memory cell of increasing pulse height to change the resistance state from the lower resistance state to the higher resistance state. The fixed sequence of voltage pulses cause increasing current through the phase change memory element until change to the higher resistance state occurs, and after the change the voltage pulses in the fixed sequence causing a voltage across the phase change memory element less than the threshold voltage.

Abstract: A multi-level cell copyback program method in a non-volatile memory device is disclosed. The method includes performing a multi-level cell copyback program operation; performing selectively a first verifying operation, a second verifying operation or a third verifying operation in accordance with data stored in an MSB node of the first register or data stored in an LSB node of the second register. The first verifying operation is based on a first verifying voltage. The second verifying operation is based on a second verifying voltage higher than the first verifying voltage. And the third verifying operation is based on a third verifying voltage higher than the second verifying voltage. The copy back program operation is performed repeatedly in accordance with result of the verifying operation.

Abstract: At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and is required for crystallizing the element is applied thereto. And, the magnitude of this voltage Vset is then changed depending on the ambient temperature so that the magnitude of the voltage Vset is small as the temperature becomes high (TH). In this manner, a margin of a write operation between the set operation and a reset operation (RESET) for making the element to be in amorphous state is improved.

Abstract: The present disclosure includes systems and techniques relating to non-volatile memory. The systems and techniques can include accessing a threshold value that is associated with a data area of a non-volatile memory structure, performing a comparison using the threshold value and a first value associated with the data area, and selectively reprogramming data of the data area based on the comparison. A programming operation on the data area can trigger a reset of the first value. Accessing a threshold value can include accessing a second value that reflects a count of programming operations on the data area or a time between programmings and using the second value to select the threshold value.

Abstract: A command processing circuit for generating internal command signals corresponding to a plurality of unit internal command signals sequentially applied during a plurality of command cycles, the command processing circuit includes a first command latching unit configured to latch a first unit internal command signal applied in a first command cycle and a second command latching unit configured to latch a second unit internal command signal in response to the first unit internal command signal latched in the first command latching unit in a second command cycle after the first command cycle, and output an internal command signal corresponding to the first unit internal command signal and the second unit internal command signal.