Patents Examined by Trong Phan
  • Patent number: 8264880
    Abstract: The present disclosure includes systems and techniques relating to non-volatile memory. A described device includes a non-volatile memory structure including a first data area, and a second data area that stores information. The information can include a first value corresponding to the first data area, the first value being set responsive to a last programming cycle on the first data area, and a second value indicating a total number of programming or erasing operations on the first data area.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: September 11, 2012
    Assignee: Marvell International Ltd.
    Inventor: Xueshi Yang
  • Patent number: 8259499
    Abstract: Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: September 4, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Yi-Fan Chang, Su-chueh Lo, Cheng Ming Yih, Ta Kang Chu, Chu Ching Wu, Kuo Yu Liao, Ken Hui Chen, Kuen-Long Chang, Chun-Hsiung Hung
  • Patent number: 8254184
    Abstract: A semiconductor memory device includes a latency controller which provides a power-saving effect. The latency controller includes a first-in first-out (FIFO) register. After a read command is applied, when a precharge command or power-down command is applied, the latency controller outputs a latency signal corresponding to the applied read command and blocks application of sampling and transmission clock signals to the FIFO register.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: August 28, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Soo Sohn, Jeong-Don Lim, Kwang-Il Park
  • Patent number: 8254168
    Abstract: According to one embodiment, a semiconductor device includes memory cells, bit lines, a write circuit, and sense amplifiers. The bit lines are connected to the memory cells. The sense amplifiers are configured to bias the bit line to which the selected memory cell is connected, to a first voltage until the threshold of the selected memory cell reaches the value of a first write state. Then, when the threshold of the selected memory cell reaches the value of the first write state, the bit line is biased to a second voltage higher than the first voltage. When the threshold of the selected memory cell reaches the value of a second write state, the bit line is continuously biased to a third voltage higher than the second voltage. Bit lines connected to unselected memory cells corresponding to the memory cells other than the selected one are biased to the third voltage.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: August 28, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuya Suzuki, Rieko Tanaka
  • Patent number: 8248852
    Abstract: A nonvolatile memory device includes a first address decoder and a second address decoder. The first address decoder includes a plurality of transistors disposed in a first well, and the second address decoder includes a plurality of transistors disposed in a second well that is electrically isolated from the first well. The first and second address decoders are associated with first and second memory blocks, respectively. A switch circuit is configured to provide a negative voltage to one of the first address decoder and the second address decoder on the basis of block address information that specifies an address included in one of the first memory block and the second memory block. Related methods of operation are also discussed.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: August 21, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moosung Kim, Youngho Lim
  • Patent number: 8250282
    Abstract: A memory controller for a phase change memory (PCM) that can be used on a storage bus interface is described. In one example, the memory controller includes an external bus interface coupled to an external bus to communicate read and write instructions with an external device, a memory array interface coupled to a memory array to perform reads and writes on a memory array, and an overwrite module to write a desired value to a desired address of the memory array.
    Type: Grant
    Filed: May 14, 2009
    Date of Patent: August 21, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Emanuele Confalonieri, Manuela Scognamiglio, Federico Tiziani
  • Patent number: 8250283
    Abstract: According to one general aspect, a method may include receiving, from a processor at an I/O controller, a write-distribute command that includes an indication of data to be written to a group of storage mediums and instructions that the data should be written to multiple storage locations within the group of storage mediums. In various embodiments, the method may also include, based on the command's instructions, writing the data to at least a first storage location of the storage mediums. In one embodiment, the method may include returning a write completion message, from the I/O controller to the processor, after the data is written to a first storage location.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: August 21, 2012
    Assignee: Google Inc.
    Inventors: Jung-Ik Lee, Grant Grundler
  • Patent number: 8243531
    Abstract: There is provided a reference potential generating circuit of a semiconductor memory, including: a first MOS transistor group that includes a plurality of first MOS transistors that are connected in series; a second MOS transistor that is connected in series to the first MOS transistor group; a third MOS transistor that is connected in parallel to the circuit in which the first MOS transistor group and the second MOS transistor are connected in series, has a gate connected to a connection point of the first MOS transistor group and the second MOS transistor, and corrects a reference potential from a connection point of the first MOS transistors; and a fourth MOS transistor that is connected to the gate of the third MOS transistor, and decreases the potential of the gate of the third MOS transistor when a permission signal to supply power to the semiconductor memory is input.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: August 14, 2012
    Assignee: OKI Semiconductor Co., Ltd.
    Inventor: Akihiro Hirota
  • Patent number: 8238141
    Abstract: Some embodiments regard a circuit comprising a memory cell, a first data line, a second data line, a sensing circuit coupled to the first data line and the second data line, a node selectively coupled to at least three voltage sources via at least three respective switches, a fourth switch, and a fifth switch. A first voltage source is configured to supply a retention voltage to the node via a first switch. A second voltage source is configured to supply a ground reference voltage to the node via a second switch, and a third voltage source is configured to supply a reference voltage to the node via a third switch. The fourth switch and fifth switch are configured to receive a respective first control signal and second control signal and to pass a voltage at the node to the respective first data line and second data line.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: August 7, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Atul Katoch, Cormac Michael O'Connell
  • Patent number: 8238140
    Abstract: A memory wherein the bit reliability of the memory cells can be dynamically varied depending on the application or the memory status, the operation stability is ensured, and thereby a low power consumption and a high reliability are realized. Either a mode (a 1-bit/1-cell mode) in which one bit is composed of one memory cell or a mode (a 1-bit/n-cell mode) in which one bit is composed of n (n is two or more) connected memory cells is dynamically selected. When the 1-bit/n-cell mode is selected, the read/write stability of one bit is enhanced, the cell current during read is increased (read is speeded up), and a bit error, if occurs, is self-corrected. Especially, a pair of CMOS transistors and a control line for performing control so as to permit the CMOS transistors to conduct are added between the data holding nodes of n adjacent memory cells. With this, the word line (WL) is controlled, and thereby the operation stability is further improved.
    Type: Grant
    Filed: January 7, 2009
    Date of Patent: August 7, 2012
    Assignee: The New Industry Research Organization
    Inventors: Masahiko Yoshimoto, Hiroshi Kawaguchi, Shunsuke Okumura, Hidehiro Fujiwara
  • Patent number: 8238178
    Abstract: A memory circuit includes a first group of memory arrays including a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface. A second group of memory arrays include a third memory array coupled with a third IO interface and a fourth memory array coupled with a fourth TO interface. A plurality of redundancy bit lines include at least one first redundancy bit line that is configured for selectively repairing the first group of memory arrays, and at least one second redundancy bit line that is configured for selectively repairing the second group of memory arrays.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: August 7, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tien-Chun Yang, Yue-Der Chih, Shang-Hsuan Liu
  • Patent number: 8238158
    Abstract: An electrically programmable non-volatile memory array and associated circuitry, including programming circuitry that adaptively senses completed programming of a selected memory cell. A programming bit line driver is connected to the bit line, and a first transistor has its source/drain path connected in series with the memory cell, and its gate connected to the output of the current comparator. As the MOS transistor in the selected cell becomes programmed, its drain current drawn from the bit line driver decays, and a remainder current into the current comparator increases. Upon the remainder current exceeding the reference current, the comparator turns off the first transistor; a second transistor connected between the source and drain of the cell transistor is turned on. In another approach, a summed current controls the gates of the first and second transistors. Programming terminates, and over-programming is avoided.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: August 7, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Douglas Edward Shelton, Bruce Lynn Pickelsimer, John Howard MacPeak
  • Patent number: 8233310
    Abstract: According to one embodiment, a resistance-change memory includes bit lines running in a first direction, word lines running in a second direction, and a memory cell array includes memory cells each includes a selection transistor and a variable resistance element. In a layout of first to fourth variable resistance elements arranged in order in the first direction, the first variable resistance element and the second variable resistance element sandwich one word line therebetween, the third variable resistance element and the fourth variable resistance element sandwich one word line therebetween, a first pair includes the first and second variable resistance elements and a second pair includes the third and fourth variable resistance elements sandwich two word lines therebetween, and a column is constructed by repeating the layout in the first direction.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: July 31, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuyuki Fujita, Shinichiro Shiratake
  • Patent number: 8228702
    Abstract: The present disclosure concerns a magnetic random access memory-based ternary content addressable memory cell, comprising a first and second magnetic tunnel junction respectively connected to a first and second straps extending on each side of the first and second magnetic tunnel junctions, respectively; a first and second selection transistors, respectively connected to one extremity of the first and second straps; a first and second current lines; and a conductive line electrically connecting in series the first and second magnetic tunnel junctions at their ends opposed to the ones connecting the first and second straps. The cell disclosed herein has smaller size and can be advantageously used in memory devices having a high cell density array.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: July 24, 2012
    Assignee: Crocus Technology SA
    Inventors: Virgile Javerliac, Mourad El Baraji
  • Patent number: 8223524
    Abstract: A multi-chip package memory includes an interface chip generating at least one reference signal defined in relation to a reference process variation, and a stacked plurality of memory chips electrically connected to the interface chip via a vertical connection path and receiving the reference clock signal via the vertical connection path, wherein each one of the stacked plurality of memory chips is characterized by a process variation and actively compensates for said process variation in relation to the reference signal.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: July 17, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hoe-ju Chung
  • Patent number: 8223577
    Abstract: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: July 17, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Takesada Akiba, Shigeki Ueda, Toshikazu Tachibana, Masashi Horiguchi
  • Patent number: 8218364
    Abstract: An integrated circuit includes a memory array having a plurality of memory cells arranged in rows and columns, each memory cell including two doped regions and a channel region therebetween, each pair of adjacent memory cells sharing a common doped region, each memory cell having a charge storage member over the channel region and a control gate over the charge storage member. A first word line is coupled to the memory cells in the same row, each of the memory cells designated as the Nth memory cell. Each of a plurality of bit lines is designated as the Nth bit line, the Nth bit line coupled to a doped region shared by the Nth memory cell and the (N?1)th memory cell. The integrated circuit also has a plurality of global bit lines, each of which coupled to two of the bit lines via a switch.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: July 10, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Lit-Ho Chong, Wen-Jer Tsai, Tien-Fan Ou, Jyun-Siang Huang
  • Patent number: 8213250
    Abstract: A semiconductor memory device includes a cell array including a plurality of unit cells, a first amplification circuit amplifying an input signal received from at least one unit cell among the unit cells, a signal transmission unit to transmit the signal to the first amplification circuit in response to a selection signal, first amplification control circuit to output a first amplification control signal controlling an amplification operation of the first amplification circuit, a second amplification circuit to amplify an output signal of the first amplification circuit, a second amplification control circuit to output a second amplification control signal controlling an amplification operation of the second amplification circuit, and a voltage adjustment circuit to adjust an internal voltage of the first amplification circuit in response to a voltage adjustment signal before the first and second amplification circuits perform the amplification operation.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: July 3, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Keun Soo Song
  • Patent number: 8213209
    Abstract: In a method of manufacturing a semiconductor device, element properties of an element property extraction pattern formed on a semiconductor wafer is extracted as element properties of a current control element corresponding to the element property extraction pattern. A supply energy to the current control element is set which is formed between nodes on the semiconductor wafer, based on the extracted element properties. The set supply energy is supplied to the current control element to irreversible control an electrical connection between the nodes through the device breakdown by the current control element.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: July 3, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Tsuda, Yoshitaka Kubota, Hiromichi Takaoka
  • Patent number: 8212181
    Abstract: A welding gun driving device is provided with an electric motor, a feed screw mechanism, and a pressure rod axially moved forward and backward via the feed screw mechanism by the electric motor. A rotor of the electric motor is formed into a hollow shape through which the pressure rod is insertable. The feed screw mechanism is provided with a screw shaft fixed to the rotor concentrically with the rotor, and a nut portion screwed to the screw shaft. The pressure rod is provided with the nut portion and a hollow rod portion extending toward the axial front from the nut portion. The rotor is provided, at its inner peripheral face, with a guide portion through which the pressure rod is inserted and supported so as to be relatively rotatable and axially slidable.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: July 3, 2012
    Assignee: Honda Motor Co., Ltd.
    Inventors: Koichi Matsumoto, Hiroshi Miwa, Teruaki Kobayashi