Abstract: An electrically erasable programmable read-only memory device comprises a substrate having an active region, a field isolation region for isolating the active region, and extension areas integrally extended and interconnected at portions of the active region in the neighborhood of a tunnel region to enlarge an overlap margin between the active region and tunnel region. A tunnel ion implanted region is formed in a portion of the active region including the tunnel region and a tunnel dielectric film is formed on a portion of the active region corresponding to the tunnel region. A gate dielectric film is formed on the remaining portion of the active region except for the portion corresponding to the tunnel region. A floating gate is formed in common on the tunnel region and active region and a control gate is formed on the floating gate via an insulating film. A selection gate is formed on the gate dielectric film at a predetermined distance from the control gate.

Abstract: A system and method employing a rate 24/25 (0,9) code constructed in accordance with a data byte interleaved with a rate 16/17 (0,5) codeword formed from two data bytes limits the number of consecutive zeros seen by a channel to nine. The 16/17 (0,5) codeword is formed from the two data bytes in accordance with a set of pivot bits and a set of corrections for predefined code violations. The additional data byte is interleaved into the 16/17 (0,5) codeword by splitting the byte into a pair of portions and inserting the portions into the 16/17 (0,5) codeword at locations adjacent to predefined ones of the pivot bits. The rate 24/25 (0,9) code is suitable for magnetic or similar recording media and may be employed in partial response maximum likelihood read channels. A feature of the constructed code is a high transition density which allows for more frequent timing and gain control updates, which results in lower required channel input signal to noise ratio for a given channel performance.

Abstract: A column amplifier for high fixed pattern noise reduction. The column amplifier includes a switching capacitor amplifier, a sample and hold stage, and an output buffer. The switching capacitor amplifier receives signals from a bit line that is coupled to a column of active pixel sensors. The switching capacitor amplifier is capacitively coupled to the bit line from a column of active pixel sensors and is able to cancel the common mode offset in the bit line. The common mode can also be adjusted in the switching capacitor amplifier, such that the last stage of the column amplifier (e.g., the buffer stage) is not limited by the common mode level of the active pixel sensors. The switching capacitor amplifier includes an input capacitor and a feedback capacitor. The gain of the switching capacitor amplifier amplifies the pixel signals so that the fixed pattern noise introduced by stages after the switching capacitor amplifier will comprise a lower proportion of the total signal.

Abstract: A method for writing data to non-volatile memory (50) involves alternately applying programming and erase voltages to a control gate wordline of a memory cell. A write includes programming and erasing bits (30, 31, . . . , 32, 33) in the memory array (56). After writing, a verify erase (VE) operation and a verify program (VP) operation are performed to determine if multiple cycles are necessary. The method also permits refreshing data in the array without transferring the data onto a data bus for improved security. In one embodiment, a three transistor EEPROM is written by providing a high voltage to the drain select of the selected wordline, while providing a low voltage to the drain select of other wordlines. Programming and erase voltages are applied to the control gate wordline of the selected wordline in cycles until the write is complete. The memory cell structure allows isolation of each bit in the array to avoid adverse effects on neighbor bits.

Abstract: The present invention concerns a memory structure wherein a plurality of memory cells such as SRAM are provided in columns and a plurality of bit line pairs are provided for each column. A write circuit drives a first bit line pair and writes data to the memory cells in the column; at the same time, a sense amp reads data by means of the second bit line pair. In that case, the first bit line pair and second bit line pair, provided in the same column, are driven with opposite phase signals. To prevent the reversal of the small potential difference of the second bit line pair for reading at that time, two bit lines, one bit line from the first and second bit line pairs, are arranged parallel in a first wiring layer and are interspersed with a fixed potential wiring. Furthermore, the two other bit lines from the first and second bit line pairs, are arranged parallel in a second wiring layer provided via an insulating layer and are interspersed with a fixed potential wiring.

Abstract: A semiconductor memory is provided with a memory cell, a driver circuit driving the memory cell, a first word line and a second word line. The first word line is connected to the driver circuit and transmits a first potential and a second potential outputted by the driver circuit to the memory cell. The second word line is connected to the driver circuit and transmits the first potential and the second potential to the memory cell. The second word line has a resistance higher than that of the first word line. In this way, even if a word line is broken, a multiple selection phenomenon is not incurred.

Abstract: The present invention provides a method of sensing data in a semiconductor device. First, an equalizing instructing signal is provided to stop precharging and equalizing the bit line pair while in a reading state. Then a wordline is selected to transmit the data in a memory cell to one of the pair of bit lines for obtaining a potential difference between the bit line pair. A sensing enable signal is subsequently provided to activate the shared sense amplifier for sensing and amplifying the data. And a potential level of the selecting control signal is boosted to a boosted potential level to restore and read the data by delaying a predetermined period of time.

Abstract: A word line is connected to a control gate of memory cell transistor, and a bit line and a source line are connected to a drain and a source of the memory cell transistor, respectively. A write clock having a certain crest value is applied to the source line, and an earth potential or a power supply potential is applied to the bit line in response to a read clock having a phase which is opposite to that of the write clock. A row selection clock which synchronizes with the write clock and a crest value of which is de-escalated is applied to the word line.

Abstract: Multi-port memory arrays having partitioned registers therein are provided. The registers are partitioned into subarrays so that at least two columns of a selected register can be simultaneously written to (or read from) using first and second input/output driver circuits. These first and second input/output driver circuits are electrically coupled to respective read and write data ports at opposing ends of the memory array. Control logic and first and second input/output driver circuits are provided for writing a first portion of a word of data into a first subarray while simultaneously writing a second portion of the word of data into a second subarray. Here, the first and second portions may comprise the least significant and most significant bytes of the word of data.

Abstract: After decreasing the threshold voltages of a plurality of memory cells collectively or selectively, the presence or absence of any memory cell of which the threshold voltage has dropped below a predetermined voltage verified collectively for each of memory cell groups connected to word line (low-threshold value verification), and any memory cell of which the threshold voltage has excessively dropped is selectively written. Also, the well of each of memory cell is formed in the region of an element isolation layer for isolating it from the substrate of a memory apparatus, and a negative voltage is supplied to the memory well distributively with a positive voltage applied as a word line voltage, thus supplying them as erase operation voltages. The absolute value of the memory well voltage is set substantially equal to or lower than the word line voltage for the read operation.

Abstract: An output buffer circuit includes a pull-up section for connecting therethrough a source line Vcc and an impedance control terminal, a comparator for comparing the potential of the impedance control terminal against a potential of Vcc/2, an UP/DOWN counter for up- and down-counting clock pulses of a clock signal based on the result of the comparison, a D/A converter for converting an output from the UP/DOWN counter, an output section, connected between the source line Vcc and an output terminal, for receiving an input data signal to output an output data signal based on the input data signal. The output from the D/A converter controls both the ON-resistances of the pull-up section and the output section. The output impedance of the output buffer circuit is controlled based on the resistance of an external resistor connected between the impedance control terminal and ground.

Abstract: A drive circuit for a P-channel FET is provided which uses a switch means to bias the P-channel FET into conduction and passive components to bias the P-channel FET out of conduction, reducing the components required in the drive circuit and the power dissipated. Energy stored in an inductor while the P-channel FET is conducting is used to provide current through a capacitor in series with the gate to source capacitance of the P-channel FET reducing the stored charge and turning off the P-channel FET.

Abstract: An analog switch circuit includes an input terminal to which an analog signal is supplied, an output terminal, first, second and third transistors, and a delay circuit. The first transistor has first and second electrodes and a gate, and the first electrode of the first transistor is connected to the input terminal. The second transistor has first and second electrodes and a gate, and the first electrode of the second transistor is coupled to the first electrode of the first transistor. The gate of the second transistor is supplied with a clock signal supplied from an external circuit. The delay circuit delays the clock signal by a predetermined time and generates a delayed clock signal supplied to the gate of the first transistor. The third transistor has first and second electrodes and a gate. The first and second electrodes of the third transistor are coupled to each other and to the second electrode of the second transistor and the output terminal through which an analog output signal is output.

Abstract: A low-absorption circuit device for controlling into the on state a power transistor, in particular a D MOS transistor having conventional gate, drain, and source electrodes, and adapted to drive electrical loads by changing over from an off state to an on state in which there appears on the gate electrode a predetermined voltage value, comprises a first turn-on circuit connected to one pole of a voltage supply, a second turn-on circuit connected to another supply voltage pole, and a comparator having respective inputs connected to the gate electrode of the power transistor and to a reference voltage pole as well as respective outputs connected to each respective turn-on circuit to activate said circuits alternately based on a comparison of the gate voltage of the power transistor with the predetermined reference voltage.

Abstract: A driver circuit is provided which offers decreased input loading, increased output loading, and a high voltage output level corresponding to a logic-1. These results are achieved through the use of pull-up transistors and capacitive and resitive circuitry which allow bootstrapped voltages.

Abstract: A Schmitt trigger circuit has a first transistor for inversion having a base supplied with an input voltage. A level shift diode shifts an emitter voltage of the first transistor from a reference level, and a second transistor for switching has a collector and an emitter respectively coupled to an anode and a cathode of the level shift diode. The emitter of the second transistor is coupled to a first power source voltage. A switching part is coupled between a base of the second transistor and a second power source voltage higher than the first power source voltage, for controlling switching of the second transistor. An output circuit is coupled between the first and second power source voltages and supplied with the input voltage through the first transistor for outputting the output voltage. The switching part is controlled responsive to a voltage from the output circuit so as to close when the logic level of this voltage is the high level, thereby turning the second transistor ON.

Abstract: When processing logic signals in ECL and CMOS circuitry it is necessary to adjust the logic levels when going from one type of circuitry to another. A problem which occurs is that smearing of a logic level occurs due to poor rise and fall times in a level adjusting amplifier. The rise and fall times can be improved by the level adjusting amplifier load circuit comprising the series connection of the source-drain paths of first and second N-channel transistors (20, 22), the parasitic capacitance of the drain of the first transistor (20) at a node (23), and by connecting the gate of the second transistor (22) to the node. In operation, when the first transistor (20) is non-conductive and the node (23) is charged, the second transistor (22) is operating in the triode or linear region of its characteristic in spite of its gate being at the voltage of the node. When the first transistor (20) is rendered conductive then both transistors (20, 22) are fully conductive and the starting discharge current is high.

Abstract: An input synchronizing signal is subjected to mean DC voltage adjustment so that the mean DC voltage thereof becomes a prescribed level. The input synchronizing signal after the mean DC voltage adjustment is compared with first reference voltage which is higher than the prescribed level and second reference voltage which is lower than the prescribed level by comparators, to derive an output synchronizing signal of constant polarity and amplitude or a polarity detection output for the input synchronizing signal.

Abstract: A controllable integrator for a bipolar integrated filter includes a voltage-current-transformer, a current distribution multiplier and an integrating amplifier. The voltage-current-transformer includes two transistors having their emitters connected via a converting resistor and two current sources each connected to a respective one of the emitters of the two transistors. The current distribution amplifier includes two logarithmic diodes each connected to a respective one of the collectors of the two transistors, a differential stage having differential inputs connected to the two logarithmic diodes, a controllable current source for supplying current to the differential stage, and a current mirror having an output and comprising two transistors of one conductivity type having emitters connected to a source of supply voltage and collectors connected to the output of the differential stage.

Abstract: A light gate array in which each of the gates is individually controllable. Uniform light is gated through the array to form a dot-matrix image on a photosensitive material. The light gates have differing areas or shapes so that different light intensities are gated by the different gates. The array is useful when the same area of the photo-sensitive material is selectively exposed through multiple gates of different areas or shapes.