Abstract: A lumped-parameter, electrical delay line having shunt capacitance including variable-capacitance diodes. A tuning voltage applied to the diodes provides electrically variable delay at low jitter and stable insertion delay.

Abstract: A gate circuit is configured to output a received signal via a buffer amplifier, enter the output in a storage capacitor via a first switching circuit normally taking its off-position, compare the signal levels at both ends of the switching circuit and feed back the comparison result to an input terminal via a second switching circuit normally taking its on-position, and configured so that when noise components in the received signal are detected, a control signal is produced to change the first switching circuit to its on-position and the second switching circuit to its off-position.

Abstract: A Hall device is formed from a generally rectangular body of material exhibiting the Hall effect, with two excitation electrodes disposed along opposite edges of the device. Two Hall output voltage electrodes are disposed along one of the remaining edges of the main body and at least one additional output electrode is disposed on the edge of the main body opposite the first pair of electrodes. At least two of the output electrodes are offset from a centerline drawn through the electrical midpoint of the main body. By deliberately offsetting the Hall voltage output electrodes from the centerline the first and second order voltage offsets due to inhomogeneities of the Hall material and mask misalignment are eliminated or easily compensated.

Abstract: A circuit for comparing first and second binary coded digital data signals has a plurality of first circuits each including first and second transistors of a P-channel type connected in series between a first potential terminal and a first output node, a plurality of second circuits each including third and fourth transistors of an N-channel type connected in series between a second potential terminal and a second output node, and means for precharging the first and second output nodes to first and second logic levels, respectively. The first and third transistors are supplied with one bit data of the first signal, and the second and fourth transistors are supplied with an inverted data of the second signal. A change in the logic level at least one of the first and second output nodes is detected.

Abstract: A semiconductor switching device includes a row of a plurality of switching elements connected in series. The input terminal of the input-nearest switching element and the output terminal of the output-nearest switching element are connected with the input terminal and output terminal of the semiconductor switching device, respectively. A control signal is applied to the control terminal of the output-nearest switching element. The semiconductor switching device comprises a first plurality of capacitive elements each of which is connected between the output terminal of the output-nearer switching element and the control terminal of the input-nearer switching element of the adjacent switching elements among the switching element row; and a second capacitive element connected between the output terminal and input terminal of the input-nearest switching element. At least the switching elements (S.sub.2 -S.sub.n) have insulating gates, respectively.

Abstract: A static relay for direct voltages. A load (Z) is energized via the collector of an output transistor (T.sub.s) of the pnp type. The state of the relay and that of the load are detected by a first bipolar detection transistor (T.sub.c1) having its base-emitter path, to which a base resistor (R.sub.b) is added, connected parallel to the base-emitter path of the output transistor (T.sub.s). A second detection transistor (T.sub.c2) of the MOSFET type has its drain connected to the collector of the first detection transistor (T.sub.c1) and its gate connected to the collector of the output transistor (T.sub.s). The source electrode of the second detection transistor constitutes a detection terminal (C) which, when it is loaded by a resistor (R.sub.c), delivers a voltage (V.sub.c) of high level in the case of normal operation of the relay.

Abstract: A method and means are provided for increasing the frequency of update of direction information contained in two essentially identical alternating current signals, essentially sinusoidal in waveform, and in quadrature. Eight electrical signals having rectangular waveforms are generated from the two primary signals. The eight signals are differentiated and the eight derivatives combined with the eight signals into two sets of eight additive pairs each, with a high level logic signal from one set indicating one direction and a high level logic signal from the other set indicating the opposite direction. The direction information is updated eight times during each full cycle of each of the two primary signals.