Abstract: A packaged ultraviolet light-emitting device includes a support member, at least one ultraviolet light-emitting chip, and an encapsulating cover. The support member has opposite top and bottom surfaces, a side surface interconnecting the top and bottom surfaces, and at least one indentation. The ultraviolet light-emitting chip is disposed on the top surface of the support member. The encapsulating cover is made from a fluorine-containing resin, and is disposed over and in contact with the ultraviolet light-emitting chip and the top surface and the indentation of the support member. The encapsulating cover extends into the indentation. A production method of the packaged ultraviolet light-emitting device is also disclosed.

Abstract: An optical component packaging structure is provided. The optical component packaging structure includes a substrate, a far-infrared sensor chip, a metal covering cap and a light filter. The far-infrared sensor chip is disposed on the substrate and electrically connected to the substrate. The metal covering cap is disposed on the substrate and accommodating the far-infrared sensor chip. The metal covering cap has an opening exposing the far-infrared sensor chip. The light filter is disposed out of the opening and on the inner surface for covering the opening to filter the far-infrared light passing through. The far-infrared sensor chip is surrounded by the metal covering cap, the substrate and the light filter, and the metal covering cap is directly connected with the substrate.

Abstract: A package-on-package (PoP) semiconductor package includes an upper package and a lower package. The lower package includes a first semiconductor device in a first area, a second semiconductor device in a second area, and a command-and-address vertical interconnection, a data input-output vertical interconnection, and a memory management vertical interconnection adjacent to the first area.

Abstract: A composition for an organic optoelectronic device, an organic optoelectronic device including the same, and a display device, the composition including a first compound represented by a combination of Chemical Formula 1 and Chemical Formula 2, and a second compound represented by a combination of Chemical Formula 3 and Chemical Formula 4:

Abstract: A nitride-based semiconductor device includes a buffer, a first nitride-based semiconductor layer, a shield layer, a second nitride-based semiconductor layer, a pair of S/D electrodes, and a gate electrode. The first nitride-based semiconductor layer is disposed over the buffer and forms a first interface with the buffer. The shield layer includes a first isolation compound and is interposed between the buffer and the first nitride-based semiconductor layer. The first isolation compound has a bandgap greater than a bandgap of the buffer and greater than a bandgap of the first nitride-based semiconductor layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap less than the bandgap of the first isolation compound and greater than the bandgap of the first nitride-based semiconductor layer. The S/D electrodes and a gate electrode are disposed over the second nitride-based semiconductor layer.

Abstract: A 3D semiconductor device including: a first level including a single crystal layer, and a memory control circuit which includes at least one temperature sensor circuit and first transistors; a first metal layer overlaying the first single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors—which may include a metal gate—disposed atop the third metal layer; third transistors disposed atop the second transistors; a fourth metal layer disposed atop the third transistors; a memory array including word-lines and at least four memory mini arrays (each mini array includes at least four rows by four columns of memory cells), each memory cell includes at least one second transistor or at least one third transistor; and a connection path from fourth metal to third metal, the path includes a via disposed through the memory array.

Abstract: A phosphor substrate having at least one light emitting element mounted on one surface, includes an insulating substrate, at least one electrode pair disposed on one surface of the insulating substrate and bonded to the light emitting element, and a phosphor layer disposed on one surface of the insulating substrate, including a phosphor in which a light emission peak wavelength, in a case where light emitted by the element is used as excitation light, is in a visible light region, in which a bonded surface of the electrode pair facing an outer side in a thickness direction of the insulating substrate, the bonded surface being bonded to the light emitting element, is positioned further on the outer side in the thickness direction than a non-bonded surface other than the bonded surface, and at least a part of the phosphor layer is disposed around the bonded surface of the one surface.

Abstract: A method of manufacturing a semiconductor package includes forming a first redistribution structure, forming a plurality of conductive pillars on the first redistribution structure, mounting the first semiconductor chip on the first redistribution structure, forming an encapsulant configured to cover an upper surface of the first redistribution structure, the plurality of conductive pillars, and the first semiconductor chip, planarizing the encapsulant, exposing the plurality of conductive pillars by forming an opening in the planarized encapsulant, and forming a second redistribution structure connected to the plurality of conductive pillars on the first semiconductor chip and the encapsulant. Upper surfaces of the plurality of conductive pillars are located at a lower level than the upper surface of the first semiconductor chip, and an upper surface of a connection via included in the second redistribution structure has a width greater than a width of a lower surface of the connection via.

Abstract: An interconnection structure and a method of manufacturing the same, and an electronic device including the interconnection structure are provided.

Abstract: A 3D device, the device including: at least one first level including logic circuits; at least one second level bonded to the first level, where the at least one second level includes a plurality of transistors; connectivity structures, where the connectivity structures include a plurality of transmission lines, where the plurality of transmission lines are designed to conduct radio frequencies (“RF”) signals, and where the bonded includes oxide to oxide bond regions and metal to metal bond regions; and a plurality of vias disposed through the at least one second level, where at least a majority of the plurality of vias have a diameter of less than 5 micrometers.

Abstract: A package structure includes at least one semiconductor die, an insulating encapsulant and a redistribution structure. The at least one semiconductor die has a plurality of conductive posts, wherein a top surface of the plurality of conductive posts has a first roughness. The insulating encapsulant is encapsulating the at least one semiconductor die. The redistribution structure is disposed on the insulating encapsulant in a build-up direction and is electrically connected to the at least one semiconductor die. The redistribution structure includes a plurality of conductive via portions and a plurality of conductive body portions embedded in dielectric layers, wherein a top surface of the plurality of conductive body portions has a second roughness, and the second roughness is greater than the first roughness.

Abstract: Provided is a display substrate, including: a base substrate, a light emitting structure layer disposed on the base substrate, and a color filter layer disposed on the light emitting structure layer; the base substrate having a display area and a peripheral area located at a periphery of the display area, the display area including multiple pixel driving circuits connected with the light emitting structure layer in the display area, the pixel driving circuit including a transistor which includes an active layer located in an interior of the base substrate; the color filter layer including a transition structure, the transition structure of the color filter layer being located between the display area and the peripheral area of the base substrate.

Abstract: An alternating stack of first material layers and second material layers is formed over a substrate. A hard mask layer is formed over the alternating stack. Optionally, an additional hard mask layer can be formed over the hard mask layer. A photoresist layer is applied and patterned, and cavities are formed in the hard mask layer by performing a first anisotropic etch process that transfers a pattern of the openings in the photoresist layer through the hard mask layer. Via openings are formed through an upper portion of the alternating stack by performing a second anisotropic etch process. A cladding liner can be optionally formed on sidewalls of the cavities in the hard mask layer. The via openings can be vertically extend through all layers within the alternating stack by performing a third anisotropic etch process.

Abstract: A semiconductor device includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants. The dopants are bonded to the noble metal material.

Abstract: A field effect transistor sensor includes: a source-drain channel, a semiconductor layer on said source-drain channel, a first gate electrode arranged above said semiconductor layer, a first well enclosing said source-drain channel, said semiconductor layer and said first gate electrode, the first well being configured to be filled, in use, with a first liquid, particularly a gating electrolyte, a second gate electrode arranged above the first gate electrode and exposed to an interior of the first well. Also disclosed is an array device including an array of field effect transistor sensors according to the above.

Abstract: The present disclosure provides a method for fabricating an integrated circuit (IC). The method includes receiving an IC layout having a first pattern layer that includes first source/drain (S/D) contacts and second S/D contacts, the first and second S/D contacts are spaced away from each other by a spacing along a first direction, and each of the first and second S/D contacts have elongated shapes extending lengthwise in a second direction perpendicular to the first direction. The method includes constructing a conductive feature on a second pattern layer of the IC layout, the conductive feature having an initial rectangular shape with a length and a width, the length extending along the first direction. And the method includes modifying the conductive feature to form a modified conductive feature that is overlapped with the first S/D contacts and distanced away from the second S/D contacts.

Abstract: The present invention relates to an organic light emitting device including: an anode; a cathode; and a light emitting light provided between the anode and the cathode, in which a first organic material layer including a composition which includes a compound of Chemical Formula 1 or a cured product thereof is included between the light emitting layer and the anode, and a second organic material layer including a composition which includes a copolymer of Chemical Formula 2 or a cured product thereof is included between the first organic material layer and the light emitting layer, Wherein all the variables are described herein.

Abstract: Techniques in accordance with embodiments described herein are directed to semiconductor devices including a layer of aluminum nitride AlN or aluminum gallium nitride AlGaN as a ferroelectric layer and a method of making a thin film of AlN/AlGaN that possesses ferroelectric properties. In a ferroelectric transistor, a thin film of AlN/AlGaN that exhibits ferroelectric properties is formed between a gate electrode and a second semiconductor layer, e.g., of GaN.

Abstract: A semiconductor device includes first and second wiring layers, and first and second via plugs. The first wiring layer has parallel tracks along which wirings are laid out, the tracks including first and second outer tracks and an inner track between the first and second outer tracks, the wirings including a first line laid out along the first outer track and having an end portion that is laid out along the first outer track, and a second line laid out along the inner track and having an end portion that is laid out along the first outer track. The first via plug is in contact with the end portion of the first line and extends between the first and second wiring layers, and the second via plug is in contact with the end portion of the second line and extends between the first and second wiring layers.

Abstract: An apparatus and configuring scheme where a ferroelectric capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the ferroelectric capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and pull-down devices are turned on in a sequence, and inputs to the capacitors are set to condition the voltage on node n1. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.