Patents Examined by Tu Tu V Ho
  • Patent number: 10811420
    Abstract: The present disclosure provides a semiconductor structure and a method for forming the semiconductor structure. The semiconductor structure includes: a polysilicon layer, having a first surface and a second surface opposite to the first surface; a substrate, disposed on the second surface of the polysilicon layer; a bit line structure, disposed on the substrate, penetrating through the polysilicon layer and protruding from the first surface of the polysilicon layer; and a spacer structure, disposed on lateral sidewalls of the bit line structure, including an air gap sandwiched by a first dielectric layer and a second dielectric layer, wherein a first portion of the second dielectric layer is in the polysilicon layer, a second portion of the second dielectric layer is outside the polysilicon layer, and a thickness of the second portion of the second dielectric layer is less than a thickness of the first portion of the second dielectric layer.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: October 20, 2020
    Assignee: Nanya Technology Corporation
    Inventors: Szu-Han Chen, Hsu Chiang, Ching-Yuan Kuo
  • Patent number: 10811328
    Abstract: A semiconductor package may include a frame including an insulation layer having a cavity formed in a lower surface of the insulation layer, a first post and a second post spaced apart from the cavity, and a metal plate disposed on an upper side of the cavity; a semiconductor chip having a first surface on which a connection pad is disposed and a second surface opposing the first surface; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure disposed on the frame and the first surface of the semiconductor chip, and including one or more redistribution layers. The first post is electrically connected to the wiring layer of the frame and the redistribution layer of the connection structure, and the second post is spaced apart from the first post.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: October 20, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Myung Sam Kang, Moon Il Kim, Young Gwan Ko
  • Patent number: 10811358
    Abstract: A semiconductor package includes an organic frame having first and second surfaces opposing each other, having a cavity, and having a wiring structure connecting the first and second surfaces, a connection structure disposed on the first surface of the organic frame and having a first redistribution layer connected to the wiring structure, at least one inorganic interposer having first and second surfaces, and having an interconnection wiring connecting the first and second surfaces of the at least one inorganic interposer to each other, an encapsulant encapsulating at least a portion of the at least one inorganic interposer, an insulating layer disposed on the second surface of the organic frame and the second surface of the at least one inorganic interposer, a second redistribution layer having portions provided as a plurality of pads, and at least one semiconductor chip having connection electrodes respectively connected to the plurality of pads.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: October 20, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO. LTD.
    Inventors: Job Ha, Sung Hyun Kim, Ji Na Jeung
  • Patent number: 10804181
    Abstract: Embodiments of the present invention relate to an heterogenous thermal interface material (TIM). The heterogenous TIM includes two or more different materials. One material has a low elastic modulus, also known as Young's modulus, and is utilized primarily to transfer heat from one component to another component. Another material has a higher elastic modulus and is primarily utilized to bond or connect the corners and/or edges of one component to the other component. The high elastic modulus material is generally located within the heterogenous TIM where TIM strain is or is expected to be high. For example, the high elastic modulus material may be located at the corner and/or edge regions of the heterogenous TIM.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: October 13, 2020
    Assignee: International Business Machines Corporation
    Inventors: Marcus E. Interrante, Sushumna Iruvanti, Shidong Li, Tuhin Sinha
  • Patent number: 10804201
    Abstract: A structure for a semiconductor device includes a dielectric layer and a metal layer. The structure also includes a plurality of unit cells. Each unit cell is formed of interconnected segments. The plurality of unit cells forms a lattice. The lattice is between the dielectric layer and the metal layer.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: October 13, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Archana Venugopal, Benjamin Stassen Cook, Nazila Dadvand, Luigi Colombo
  • Patent number: 10804363
    Abstract: Disclosed are three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor memory device comprises a substrate that includes a cell array region and a connection region, an electrode structure that includes a plurality of electrodes and a plurality of dielectric layers alternately stacked on the substrate and has a stepwise structure on the connection region, an etch stop pattern that covers the stepwise structure of the electrode structure. The electrode structure and the etch stop pattern extend in a first direction when viewed in plan. The electrode structure has a first width in a second direction intersecting the first direction. The etch stop pattern has a second width in the second direction. The second width is less than the first direction.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: October 13, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Hwang, Joon-Sung Lim, Jiyoung Kim, Jiwon Kim, Woosung Yang
  • Patent number: 10793712
    Abstract: Provided are a heat-curable resin composition for semiconductor encapsulation that is capable of yielding a cured product superior in tracking resistance and dielectric property, and has a favorable continuous moldability; and a semiconductor device encapsulated by a cured product of such resin composition. The heat-curable resin composition for semiconductor encapsulation contains: (A) an epoxy resin other than a silicone-modified epoxy resin, being solid at 25° C.; (B) a silicone-modified epoxy resin; (C) a cyclic imide compound having, in one molecule, at least one dimer acid backbone, at least one linear alkylene group having not less than 6 carbon atoms, at least one alkyl group having not less than 6 carbon atoms, and at least two cyclic imide groups; (D) an organic filler; and (E) an anionic curing accelerator.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: October 6, 2020
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Yoshihiro Tsutsumi, Naoyuki Kushihara, Norifumi Kawamura, Yuki Kudo
  • Patent number: 10790143
    Abstract: A semiconductor structure, a high electron mobility transistor (HEMT), and a method for fabricating a semiconductor structure are provided. The semiconductor structure includes a substrate, a flowable dielectric material pad layer, a reflow protection layer, and a GaN-based semiconductor layer. The substrate has a pit exposed from a top surface of the substrate. The flowable dielectric material pad layer is formed in the pit, and a top surface of the flowable dielectric material pad layer is below the top surface of the substrate. The reflow protection layer is formed on the substrate and the top surface of the flowable dielectric material pad layer. The GaN-based semiconductor layer is disposed over the substrate.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: September 29, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yung-Fong Lin, Cheng-Tao Chou
  • Patent number: 10790195
    Abstract: A method includes following steps. A semiconductor fin is formed on a substrate and extends in a first direction. A source/drain region is formed on the semiconductor fin and a first interlayer dielectric (ILD) layer over the source/drain region. A gate stack is formed across the semiconductor fin and extends in a second direction substantially perpendicular to the first direction. A patterned mask having a first opening is formed over the first ILD layer. A protective layer is formed in the first opening using a deposition process having a faster deposition rate in the first direction than in the second direction. After forming the protective layer, the first opening is elongated in the second direction. A second opening is formed in the first ILD layer and under the elongated first opening. A conductive material is formed in the second opening.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: September 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Chin Chang, Li-Te Lin, Pinyen Lin
  • Patent number: 10790269
    Abstract: Semiconductor devices and semiconductor structures are disclosed. One of the semiconductor device includes a semiconductor package and a connector. The semiconductor package includes at least one die in a die region, an encapsulant in a periphery region aside the die region and a redistribution structure in the die region and the periphery region. The encapsulant encapsulates the at least one die. The redistribution structure is electrically connected to the die. The connector is disposed on the redistribution structure in the periphery region. The connector includes a plurality of connecting elements, wherein the connector is electrically connected to the redistribution structure through the plurality of connecting elements.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Hui Lai, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Tin-Hao Kuo
  • Patent number: 10784242
    Abstract: The present disclosure provides display substrate and a fabrication method thereof, a display panel and a display device. The display substrate has a plurality of pixel regions, and includes an anode, a light-emitting layer and a cathode in each pixel region. In each pixel region, the light-emitting layer includes a plurality of light-emitting units spaced apart from each other, both the anode and the cathode are conductive layers each having an integral structure, and the plurality of light-emitting units are connected to the anode and the cathode, respectively.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: September 22, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Yuju Chen
  • Patent number: 10784415
    Abstract: Disclosed are a light-emitting device package, a manufacturing method therefor, and a vehicle lamp and a backlight unit including the same. The light-emitting device package includes: a light-emitting chip having electrode pads positioned at a lower part thereof; a wavelength conversion unit for covering at least an upper surface and lateral surfaces of the light-emitting chip; and a reflective part which covers the lateral surfaces of the light-emitting chip. Accordingly, the light-emitting device package can be miniaturized and a separate substrate for forming a lens is not required.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: September 22, 2020
    Assignee: SEOUL SEMICONDUCTOR CO., LTD.
    Inventors: Jung Hwa Jung, Seoung Ho Jung, Sung Ki Hwang
  • Patent number: 10777574
    Abstract: According to one embodiment, in a semiconductor device, a stacked body is disposed above a substrate. In the stacked body, a conductive film and an insulating layer are alternately disposed in a stacking direction. A semiconductor columnar member penetrates the stacked body in a stacking direction. An insulating film surrounds the semiconductor columnar member. The insulating film penetrates the stacked body in the stacking direction. A pattern is disposed at a position adjacent to or close to a region. The region includes a penetration plug. The penetration plug extends from a position same as or above an upper end of the stacked body to a position below a lower end of the stacked body in the stacking direction. The pattern has a quadrangular or disjoined quadrangular shape.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: September 15, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masayuki Shishido, Tatsuya Fujishima, Nozomi Kido, Tomonori Kajino
  • Patent number: 10777573
    Abstract: A semiconductor device includes a semiconductor layer containing metal atoms, a charge storage layer provided on a surface of the semiconductor layer via a first insulating film, and an electrode layer provided on a surface of the charge storage layer via a second insulating film. The thickness of the first insulating film is 5 nm or more and 10 nm or less. The concentration of the metal atoms in the semiconductor layer is 5.0×1017 [EA/cm3] or higher and 1.3×1020 [EA/cm3] or lower.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: September 15, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuta Saito, Shinji Mori, Keiichi Sawa, Kazuhisa Matsuda, Kazuhiro Matsuo, Hiroyuki Yamashita
  • Patent number: 10777448
    Abstract: Amorphous multi-component metallic films can be used to improve the performance of electronic components such as resistors, diodes, and thin film transistors. Interfacial properties of AMMFs are superior to those of crystalline metal films, and therefore electric fields at the interface of an AMMF and an oxide film are more uniform. An AMMF resistor (AMNR) can be constructed as a three-layer structure including an amorphous metal, a tunneling insulator, and a crystalline metal layer. By modifying the order of the materials, the patterns of the electrodes, and the size and number of overlap areas, the I-V performance characteristics of the AMNR are adjusted. A non-coplanar AMNR has a five-layer structure that includes three metal layers separated by metal oxide tunneling insulator layers, wherein an amorphous metal thin film material is used to fabricate the middle electrodes.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: September 15, 2020
    Assignee: AMORPHYX, INC.
    Inventor: Sean William Muir
  • Patent number: 10770449
    Abstract: An integrated circuit includes a first standard cell having a first pFET and a first nFET integrated, and having a first dielectric gate on a first standard cell boundary. The integrated circuit further includes a second standard cell being adjacent to the first standard cell, having a second pFET and a second nFET integrated, and having a second dielectric gate on a second standard cell boundary. The integrated circuit also includes a first filler cell configured between the first and second standard cells, and spanning from the first dielectric gate to the second dielectric gate. The first pFET and the second pFET are formed on a first continuous active region. The first nFET and the second nFET are formed on a second continuous active region.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fang Chen, Jhon Jhy Liaw
  • Patent number: 10770526
    Abstract: A display device includes: a substrate including a circuit layer; a first electrode on the substrate; a first pixel defining layer on the substrate and having an opening exposing an upper surface of the first electrode; a second pixel defining layer on the first pixel defining layer and comprising an amphipathic material; an organic layer on the first electrode; and a second electrode on the organic layer.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: September 8, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Min-jae Kim, Sukhoon Kang, Heera Kim, Beom-soo Shin, Hongyeon Lee
  • Patent number: 10763408
    Abstract: A backlight includes: a light-emitting module including: a base member including a conductive pattern; a plurality of light-emitting devices, each of which is flip-chip bonded on the base member and electrically connected to the conductive pattern, and each of which includes: a light-emitting element, and a dielectric multi-layer film located on an upper surface of the light-emitting element; a plurality of light reflective members arranged between the plurality of light-emitting elements; a transparent laminate located above the plurality of light-emitting devices and including: a wavelength converting member adapted to absorb a portion of light from the light-emitting elements and to emit light of a wavelength that is different from an emission wavelength of the light-emitting elements, and a diffuser plate; and a reflective member facing a lateral surface of the transparent laminate.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: September 1, 2020
    Assignee: NICHIA CORPORATION
    Inventor: Motokazu Yamada
  • Patent number: 10756003
    Abstract: A process comprises bonding a semiconductor wafer to an inorganic wafer. The semiconductor wafer is opaque to a wavelength of light to which the inorganic wafer is transparent. After the bonding, a damage track is formed in the inorganic wafer using a laser that emits the wavelength of light. The damage track in the inorganic wafer is enlarged to form a hole through the inorganic wafer by etching. The hole terminates at an interface between the semiconductor wafer and the inorganic wafer. An article is also provided, comprising a semiconductor wafer bonded to an inorganic wafer. The semiconductor wafer is opaque to a wavelength of light to which the inorganic wafer is transparent. The inorganic wafer has a hole formed through the inorganic wafer. The hole terminates at an interface between the semiconductor wafer and the inorganic wafer.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: August 25, 2020
    Assignee: Corning Incorporated
    Inventors: Daniel Wayne Levesque, Jr., Garrett Andrew Piech, Aric Bruce Shorey
  • Patent number: 10756240
    Abstract: The present disclosure provides RGB-LED packaging modules and a display screen including a substrate; a plurality of light-emitting units disposed on the substrate, each light-emitting unit including a set of RGB-LED chips; a plastic layer provided on the light-emitting units; and a virtual isolating region provided between the light-emitting units, the virtual isolating region including a black light-absorbing layer provided on the substrate. The present disclosure makes use of the black light-absorbing layer to absorb light which may cause interference among the light-emitting units. By providing the virtual isolating region and an isolating trough, and utilizing the difference of refractive index of packaging plastic and refractive index of air, light emitted by the light-emitting units can be reflected to reduce the influence of adjacent light-emitting units. A black isolating-frame is filled in the isolating trough to minimize the interference among the light-emitting units.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: August 25, 2020
    Assignee: Shandong Jierunhong Optoelectronics Co., Ltd.
    Inventors: Shaoli Li, Changhui Sun, Yiping Kong