Patents Examined by Tu Tu V Ho
  • Patent number: 11189649
    Abstract: A photoelectric conversion apparatus, comprising: a photoelectric conversion unit; a charge accumulation unit configured to accumulate charges generated in the photoelectric conversion unit; and a transfer transistor configured to connect the photoelectric conversion unit and the charge accumulation unit to each other and to perform a transfer operation of a charge from the photoelectric conversion unit to the charge accumulation unit, wherein the photoelectric conversion apparatus outputs: a first signal obtained by performing an on-off operation of the transfer transistor a plurality of times in a state where the charge accumulation unit is accumulating charges; and a second signal obtained by performing an on-off operation of the transfer transistor a plurality of times in a state where the charge accumulation unit is not accumulating charges.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: November 30, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasushi Iwakura, Tomoya Onishi
  • Patent number: 11175447
    Abstract: An optical system includes an optical waveguide, a micro light emitting diode (micro-LED) configured to emit at least partially polarized light, and a waveguide coupler configured to couple the at least partially polarized light from the micro-LED into the optical waveguide with a coupling efficiency higher than a coupling efficiency of the waveguide coupler for unpolarized light. The micro-LED includes a substrate including a hexagonal lattice and having a first surface parallel to a semi-polar plane of the hexagonal lattice, and a plurality of layers grown on the first surface. The plurality of layers includes an active layer that includes a III-nitride material and has a top surface parallel to the semi-polar plane and the first surface of the substrate, such that the light emitted by the micro-LED is at least partially polarized and can be more efficiently coupled into the optical waveguide.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: November 16, 2021
    Assignee: FACEBOOK TECHNOLOGIES, LLC
    Inventors: Christopher Pynn, Anneli Munkholm, Hee Yoon Lee
  • Patent number: 11177234
    Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a self-assembled monolayers (SAM) layer. The package substrate includes a SAM layer on portions of a conductive pad, where the SAM layer includes light-reflective moieties. The package substrate also includes a via on a surface portion of the conductive pad, and a dielectric on and around the via, the SAM layer, and the conductive pad, where the SAM layer surrounds and contacts a surface of the via. The SAM layer may be an interfacial organic layer. The light-reflective moieties may include a hemicyanine, a cyclic-hemicyanine, an oligothiophene, and/or a conjugated aromatic compound. The SAM layer may include a molecular structure having a first end group of a first monolayer, an intermediate group, a fifth end group of a second monolayer, and one or more of a first and second light-reflective moieties.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Suddhasattwa Nad, Rahul Manepalli, Marcel Wall
  • Patent number: 11177224
    Abstract: A flat plate frame is formed, which is flat plate-shaped, which has an opening penetrating its front and rear surfaces and groove terminal patterns formed on its front surface, and which contains a semi-cured thermosetting resin. Then, an insulating substrate is disposed on the rear surface so as to cover the opening of the flat plate frame, external connection terminals are disposed on the terminal patterns, and heating is carried out. As a result, a terminal package to which the insulating substrate and external connection terminals are firmly joined is produced using the flat plate frame. The external connection terminals included in the terminal package are reliably and firmly joined to the terminal package. Therefore, the external connection terminals are not displaced when wires are bonded to the external connection terminals.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: November 16, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Toshio Denta, Yuji Ichimura
  • Patent number: 11177210
    Abstract: An integrated circuit includes functional structures and non-functional structures. The functional structures include one or more functional metal structures. The non-functional structures include one or more non-functional metal structures. At least one of the one or more non-functional metal structures is connected to at least one of the one or more functional metal structures. For example, the at least one non-functional metal structure is connected to the at least one functional metal structure through a via. Alternatively, the at least one non-functional metal structure is connected to the at least one functional metal structure by physically contacting the at least one functional metal structure without using a via.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: November 16, 2021
    Assignee: NXP B.V.
    Inventors: Sven Trester, Tobias Richard Erich Nink
  • Patent number: 11170846
    Abstract: A transmon qubit comprising a plate capacitor comprising a first plate (202) and a second plate (203) wherein the first plate is disposed opposite to at least a part of the second plate, wherein the first plate and the second plate are connected via a nonlinear inductance element (304), and a capacitance (205) formed between the first plate and the second plate, wherein the first plate and the second plate are configured to form a vacuum gap capacitor.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: November 9, 2021
    Assignee: Technische Universiteit Delft
    Inventors: Sal Jua Bosman, Gary Alexander Steele
  • Patent number: 11164943
    Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: November 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung Gil Yang, Dong Il Bae, Chang Woo Sohn, Seung Min Song, Dong Hun Lee
  • Patent number: 11164782
    Abstract: A method of fabricating a semiconductor device includes forming a plurality of semiconductor fins upon a substrate, forming a plurality of epitaxially grown source-drain regions upon the fins, forming a plurality of device gates upon the fins, the device gates disposed between the epitaxially grown source-drain regions, forming a trench exposing at least one epitaxially grown source-drain region, masking at least a portion of the exposed epitaxially grown source-drain region, forming a gate trench exposing at least a portion of a device gate and gate spacer, forming a metallization layer between the epitaxially grown source-drain region and the device gate, selectively recessing the metallization layer, forming a conductive layer upon the metallization layer, and forming a dielectric cap above the conductive layer.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Balasubramanian S Pranatharthi Haran, Dechao Guo, Nicolas Loubet, Alexander Reznicek
  • Patent number: 11158574
    Abstract: One illustrative device disclosed herein includes a layer of insulating material with its upper surface positioned at a first level and a recessed conductive interconnect structure positioned at least partially within the layer of insulating material, wherein a recessed upper surface of the recessed conductive interconnect structure is positioned at a second level that is below the first level. In this example, the device also includes a conductive cap layer positioned on the recessed upper surface of the recessed conductive interconnect structure, wherein an upper surface of the conductive cap layer is substantially co-planar with the upper surface of the layer of insulating material and a memory cell positioned above the conductive cap layer, wherein the memory cell comprises a lower conductive material that is conductively coupled to the conductive cap layer.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: October 26, 2021
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Nicholas LiCausi, Julien Frougier, Keith Donegan, Hyung Woo Kim
  • Patent number: 11152299
    Abstract: A technique relates to an integrated circuit. A first dielectric material is formed on a layer, and a second dielectric material is formed on the first dielectric material, the second dielectric material having a different characteristic than the first dielectric material. Conductive material is formed in the first dielectric material, the second dielectric material, and the layer, the conductive material forming interconnects in the layer separated by a stack of the first dielectric material and the second dielectric material. The conductive material forms a self-aligned conductive via on one of the interconnects according to a topography of the stack, the stack of the first dielectric material and the second dielectric material electrically insulating the one of the interconnects from another one of the interconnects.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: October 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicholas Anthony Lanzillo, Christopher J. Penny, Hosadurga Shobha, Lawrence A. Clevenger, Robert Robison
  • Patent number: 11152426
    Abstract: Each memory cell in an array includes a vertical stack that comprises a bottom electrode, a memory element, and a top electrode. An etch stop dielectric layer is formed over the array of memory cells. A first dielectric matrix layer is formed over the etch stop dielectric layer. The top surface of the first dielectric matrix layer is raised in a memory array region relative to a logic region due to topography. The first dielectric matrix layer is planarized by performing a chemical mechanical planarization process using top portions of the etch stop dielectric layer. A second dielectric matrix layer is formed over the first dielectric matrix layer. Metallic cell contact structures are formed through the second dielectric matrix layer on a respective subset of the top electrodes over vertically protruding portions of the etch stop dielectric layer that laterally surround the array of vertical stacks.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Cheng-Tai Hsiao, Yen-Chang Chu, Hsun-Chung Kuang
  • Patent number: 11152592
    Abstract: A display area drilling and packaging structure includes a back plate assembly, an emitting layer having a drilling area, and a hot melted adhesive layer. The emitting layer is disposed on the back plate assembly, and an annular cutting groove surrounding the drilling is disposed on the emitting layer. The hot melted adhesive layer at least covers an edge of a mouth of the annular cutting groove away from a center. A packaging layer is disposed on the back plate assembly, the hot melted adhesive layer, and the emitting layer.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: October 19, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Penghao Gu, Chunyan Xie, Lingzhi Qian, Jiahao Zhang
  • Patent number: 11152561
    Abstract: A magnetic memory device includes a lower contact plug on a substrate, a magnetic tunnel junction pattern on the lower contact plug, a bottom electrode, which is between the lower contact plug and the magnetic tunnel junction pattern and is in contact with a bottom surface of the magnetic tunnel junction pattern, and a top electrode on a top surface of the magnetic tunnel junction pattern. Each of the bottom electrode, the magnetic tunnel junction pattern, and the top electrode has a thickness in a first direction, which is perpendicular to a top surface of the substrate. A first thickness of the bottom electrode is about 0.6 to 1.1 times a second thickness of the magnetic tunnel junction pattern.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: October 19, 2021
    Inventors: Bae-Seong Kwon, Yongjae Kim, Kyungtae Nam, Kuhoon Chung
  • Patent number: 11152305
    Abstract: Provided is a semiconductor device including a dielectric layer, a first via, a second via, a first barrier layer, and a second barrier layer. The dielectric layer has a first region and a second region. The first via is disposed in the dielectric layer in the first region. The second via is disposed in the dielectric layer in the second region. The first barrier layer lines a sidewall and a bottom surface of the first via. The second barrier layer lines a sidewall and a bottom surface of the second via. The first and second barrier layers each has an upper portion and a lower portion. The upper portion has a nitrogen doping concentration greater than a nitrogen doping concentration of the lower portion. A method of manufacturing a semiconductor device is also provided.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: October 19, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Wei-Che Hong
  • Patent number: 11139244
    Abstract: Disclosed is a semiconductor device comprising a substrate, a first dielectric layer on the substrate, a first lower conductive line in the first dielectric layer, an etch stop layer on the first dielectric layer, a via-structure that penetrates the etch stop layer and connects to the first lower conductive line, a second dielectric layer on the etch stop layer, and an upper conductive line that penetrates the second dielectric layer and connects to the via-structure. The first dielectric layer includes a dielectric pattern at a level higher than a top surface of the first lower conductive line. The upper conductive line is in contact with a top surface of the etch stop layer. The etch stop layer has at an upper portion a rounded surface in contact with the via-structure.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: October 5, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jangho Lee, Jongmin Baek, Wookyung You, Kyu-Hee Han, Suhyun Bark
  • Patent number: 11139370
    Abstract: A dielectric and isolation lower fin material is described that is useful for fin-based electronics. In some examples, a dielectric layer is on first and second sidewalls of a lower fin. The dielectric layer has a first upper end portion laterally adjacent to the first sidewall of the lower fin and a second upper end portion laterally adjacent to the second sidewall of the lower fin. An isolation material is laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin and a gate electrode is over a top of and laterally adjacent to sidewalls of an upper fin. The gate electrode is over the first and second upper end portions of the dielectric layer and the isolation material.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Chia-Hong Jan
  • Patent number: 11133459
    Abstract: According to one embodiment, a magnetic element includes a first layer and a second layer. The first layer includes a first element and a second element. The first element includes at least one selected from the group consisting of Fe, Co, and Ni. The second element includes at least one selected from the group consisting of Ir and Os. The second layer is nonmagnetic.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: September 28, 2021
    Assignees: National Institute of Advanced Industrial Science and Technology, TOHOKU UNIVERSITY, NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Takayuki Nozaki, Shinji Yuasa, Rachwal Anna Koziol, Masahito Tsujikawa, Masafumi Shirai, Kazuhiro Hono, Tadakatsu Ohkubo, Xiandong Xu
  • Patent number: 11127914
    Abstract: A light emitting device includes a plurality of unit light emitting regions on a substrate. At least one of the unit light emitting regions includes at least one pair of first and second electrodes that are spaced apart, at least one first bar-type LED in a first layer on the substrate, and at least one second bar-type LED in a second layer on the substrate. At least one of the first bar-type LED or the second bar-type LED is electrically connected between the first electrode and the second electrode.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: September 21, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyun Deok Im, Jong Hyuk Kang, Dae Hyun Kim, Joo Yeol Lee, Chi O Cho, Hyun Min Cho
  • Patent number: 11127745
    Abstract: A method of forming an apparatus comprises forming a first metal nitride material over an upper surface of a conductive material within an opening extending through at least one dielectric material through a non-conformal deposition process. A second metal nitride material is formed over an upper surface of the first metal nitride material and side surfaces of the at least one dielectric material partially defining boundaries of the opening through a conformal deposition process. A conductive structure is formed over surfaces of the second metal nitride material within the opening. Apparatuses and electronic systems are also described.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: September 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kentaro Ishii, Yongjun J. Hu, Amirhasan Nourbakhsh, Durai Vishak Nirmal Ramaswamy, Christopher W. Petz, Luca Fumagalli
  • Patent number: 11127789
    Abstract: A magnetic memory device includes a substrate including a cell region and a peripheral circuit region, lower contact plugs on the cell region, data storage structures on the lower contact plugs, and a peripheral interconnection structure on the peripheral circuit region. The peripheral interconnection structure includes a line portion extending in a direction parallel to a top surface of the substrate, and contact portions extending from the line portion toward the substrate. A height of each of the contact portions is less than a height of each of the lower contact plugs.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: September 21, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-Na Cho, Bok-Yeon Won, Oik Kwon