Abstract: A display region includes a plurality of pixel driving circuitry setting regions arranged sequentially in a first direction, and each pixel driving circuitry setting region extends in a second direction intersecting the first direction. Each display circuitry includes a plurality of subpixels in one-to-one correspondence with the pixel driving circuitry setting regions, each subpixel includes a subpixel driving circuitry and a light-emitting element coupled to each other, the subpixel driving circuitry is located in a corresponding pixel driving circuitry setting region, the light-emitting element is located at a side of the subpixel driving circuitry away from the substrate, a width of the light-emitting element is greater than a width of the corresponding pixel driving circuitry setting region in the first direction, and a length of the light-emitting element is smaller than a length of the corresponding pixel driving circuitry setting region in the second direction.

Abstract: A display and a display panel are provided. An additional VDD wire is arranged in an irregular-shaped region. The VDD wire is connected to a pixel arranged in the irregular-shaped region through a plurality of connection wires, such that the display may have a narrow side edge, and at the same time, a difference between impedances of the irregular-shaped region and a regular-shaped display region may not be large, and a display region may not be split.

Abstract: Structures and methods are provided for integrating a resistance random access memory (ReRAM) in a back-end-on-the-line (BEOL) fat wire level. In one embodiment, a ReRAM device area contact structure is provided in the BEOL fat wire level that has at least a lower via portion that contacts a surface of a top electrode of a ReRAM device area ReRAM-containing stack. In other embodiments, a tall ReRAM device area bottom electrode is provided in the BEOL fat wire level and embedded in a dielectric material stack that includes a dielectric capping layer and an interlayer dielectric material layer.

Abstract: Stacked FET devices having wrap-around contacts to optimize contact resistance and techniques for formation thereof are provided. In one aspect, a stacked FET device includes: a bottom-level FET(s) on a substrate; lower contact vias present in an ILD disposed over the bottom-level FET(s); a top-level FET(s) present over the lower contact vias; and top-level FET source/drain contacts that wrap-around source/drain regions of the top-level FET(s), wherein the lower contact vias connect the top-level FET source/drain contacts to source/drain regions of the bottom-level FET(s). When not vertically aligned, a local interconnect can be used to connect a given one of the lower contact vias to a given one of the top-level FET source/drain contacts. A method of forming a stacked FET device is also provided.

Abstract: A semiconductor package includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first semiconductor substrate, a first bonding structure and a memory cell. The second semiconductor device is stacked over the first semiconductor device. The second semiconductor device includes a second semiconductor substrate, a second bonding structure in a second dielectric layer and a peripheral circuit between the second semiconductor substrate and the second bonding structure. The first bonding structure and the second bonding structure are bonded and disposed between the memory cell and the peripheral circuit, and the memory cell and the peripheral circuit are electrically connected through the first bonding structure and the second bonding structure.

Abstract: Embodiments herein describe techniques for a memory device including at least two memory cells. A first memory cell includes a first storage cell and a first transistor to control access to the first storage cell. A second memory cell includes a second storage cell and a second transistor to control access to the second storage cell. A shared contact electrode is shared between the first transistor and the second transistor, the shared contact electrode being coupled to a source area or a drain area of the first transistor, coupled to a source area or a drain area of the second transistor, and further being coupled to a bit line of the memory device. Other embodiments may be described and/or claimed.

Abstract: A phosphor substrate having at least one light emitting element mounted on one surface, includes an insulating substrate, at least one electrode pair disposed on one surface of the insulating substrate and bonded to the light emitting element, and a phosphor layer disposed on one surface of the insulating substrate, including a phosphor in which a light emission peak wavelength, in a case where light emitted by the element is used as excitation light, is in a visible light region, in which a bonded surface of the electrode pair facing an outer side in a thickness direction of the insulating substrate, the bonded surface being bonded to the light emitting element, is positioned further on the outer side in the thickness direction than a non-bonded surface other than the bonded surface, and at least a part of the phosphor layer is disposed around the bonded surface of the one surface.

Abstract: A semiconductor device includes a first cell. The first cell is surrounded by a castle-shaped forbidden region. The first cell includes a first active region, a second active region, and at least one via. The first active region and the second active region extend along a first direction and are separated from each other along a second direction traverse to the first direction. The first active region partially overlaps an upper region of the castle-shaped forbidden region, and the second active region partially overlaps a lower region of the castle-shaped forbidden region. The at least one via is arranged outside the castle-shaped forbidden region.

Abstract: An integrated circuit includes a first transistor, a second transistor, a first power line, and a second power line. The first transistor has a first active region and a first gate structure, in which the first active region has a source region and a drain region on opposite sides of the first gate structure. The second transistor is below the first transistor, and has a second active region and a second gate structure, in which the second active region has a source region and a drain region on opposite sides of the second gate structure. The first power line is above the first transistor, in which the first power line is electrically connected to the source region of first active region. The second power line is below the second transistor, in which the second power line is electrically connected to the source region of second active region.

Abstract: A device includes an electrical circuit having a first set of circuit elements. The device further includes a first set of conductive pillars over a first side of a substrate. The device further includes a first conductive rail electrically connected to each of the first set of conductive pillars, wherein each of the first set of conductive pillars is electrically connected to each of the first set of circuit elements by the first conductive rail. The device further includes a first plurality of power pillars extending through the substrate, wherein each of the first plurality of power pillars is electrically connected to the first conductive rail.

Abstract: A semiconductor device includes a semiconductor substrate, a conductive pad disposed on the semiconductor substrate, and a pillar pattern disposed on the conductive pad. The semiconductor device further includes a solder seed pattern disposed on the pillar pattern, and a solder portion disposed on the pillar pattern and the solder seed pattern. A first width of the solder seed pattern is less than a second width of a top surface of the pillar pattern.

Abstract: A semiconductor structure includes a die and a first connector. The first connector is disposed on the die. The first connector includes a first connecting housing, a first connecting element and a first connecting portion. The first connecting element is electrically connected to the die and disposed at a first side of the first connecting housing. The first connecting portion is disposed at a second side different from the first side of the first connecting housing, wherein the first connecting portion is one of a hole and a protrusion with respect to a surface of the second side of the first connecting housing.

Abstract: A semiconductor device includes: a first insulating layer, a plurality of first electrodes penetrating the first insulating layer, a plurality of second electrodes penetrating the first insulating layer, the plurality of second electrodes being located between the plurality of first electrodes: a first high dielectric constant layer having a dielectric constant higher than a dielectric constant of the first insulating layer, a plurality of third electrodes penetrating the first high dielectric constant layer, the plurality of third electrodes being respectively connected to the plurality of first electrodes, and a plurality of fourth electrodes penetrating the first high dielectric constant layer, the plurality of fourth electrodes being located between the plurality of third electrodes.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a channel to conduct current, the channel including a first channel portion and a second channel portion, a first memory cell structure located between a first gate and the first channel portion, a second memory cell structure located between a second gate and the second channel portion, and a void located between the first and second gates and between the first and second memory cell structures.

Abstract: Devices and methods for manufacturing a deep trench capacitor fuse for high voltage breakdown defense. A semiconductor device comprising a deep trench capacitor structure and a transistor structure. The transistor structure may comprise a base, a first terminal formed within the base, and a second terminal formed within the base. The first terminal and the second terminal may be formed by doping the base. The deep trench capacitor structure may comprise a first metallic electrode layer and a second metallic electrode layer. The first terminal may be electrically connected to the first metallic electrode layer, and the second terminal may be electrically connected to the second metallic electrode layer.

Abstract: A field effect device is provided. The field effect device includes an active gate structure, a gate contact within the active gate structure, wherein the gate contact is the same height as the active gate structure, and a gate cut dielectric on opposite sides of the gate contact and active gate structure.

Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes forming a first wafer including a plurality of electronic integrated circuits (EICs), forming a second wafer including a plurality of photonic integrated circuits (PICs), bonding the first wafer to the second wafer to form a first stacked wafer. The bonding of the first wafer to the second wafer includes vertically aligning each of the plurality of the EICs with one of the plurality of the PICs.

Abstract: An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.

Abstract: A semiconductor device includes an upper section of a supervia formed via subtractive etching and a lower section of the supervia formed via damascene processing. The supervia connects non-adjacent interconnect wiring. The lower section and the upper section of the supervia each define a generally cone-shaped configuration. A distal end of the lower section of the supervia is non-obtuse. Moreover, the lower section of the supervia is formed in a V0 level and the upper section of the supervia is formed in a M1/V1 metallization level.

Abstract: A 3D device, the device including: at least a first level including logic circuits; and at least a second level bonded to the first level, where the second level includes a plurality of transistors, where the device include connectivity structures, where the connectivity structures include at least one of the following: a. differential signaling, or b. radio frequency transmission lines, or c. Surface Waves Interconnect (SWI) lines, and where the bonded includes oxide to oxide bond regions and metal to metal bond regions.