Patents Examined by Tu Tu V Ho
  • Patent number: 11996329
    Abstract: The present disclosure provides a method for fabricating an integrated circuit (IC). The method includes receiving an IC layout having a first pattern layer that includes first source/drain (S/D) contacts and second S/D contacts, the first and second S/D contacts are spaced away from each other by a spacing along a first direction, and each of the first and second S/D contacts have elongated shapes extending lengthwise in a second direction perpendicular to the first direction. The method includes constructing a conductive feature on a second pattern layer of the IC layout, the conductive feature having an initial rectangular shape with a length and a width, the length extending along the first direction. And the method includes modifying the conductive feature to form a modified conductive feature that is overlapped with the first S/D contacts and distanced away from the second S/D contacts.
    Type: Grant
    Filed: February 1, 2023
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Hsiung Wang, Bao-Ru Young, Tung-Heng Hsieh
  • Patent number: 11996451
    Abstract: Techniques in accordance with embodiments described herein are directed to semiconductor devices including a layer of aluminum nitride AlN or aluminum gallium nitride AlGaN as a ferroelectric layer and a method of making a thin film of AlN/AlGaN that possesses ferroelectric properties. In a ferroelectric transistor, a thin film of AlN/AlGaN that exhibits ferroelectric properties is formed between a gate electrode and a second semiconductor layer, e.g., of GaN.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: May 28, 2024
    Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan University
    Inventors: Miin-Jang Chen, Tzong-Lin Jay Shieh, Bo-Ting Lin
  • Patent number: 11997921
    Abstract: The present invention relates to an organic light emitting device including: an anode; a cathode; and a light emitting light provided between the anode and the cathode, in which a first organic material layer including a composition which includes a compound of Chemical Formula 1 or a cured product thereof is included between the light emitting layer and the anode, and a second organic material layer including a composition which includes a copolymer of Chemical Formula 2 or a cured product thereof is included between the first organic material layer and the light emitting layer, Wherein all the variables are described herein.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: May 28, 2024
    Assignee: LG Chem, Ltd.
    Inventors: Dowon Lim, Ji Hoon Kim, Juhwan Kim, Donghwan Lee, Jaesoon Bae, Jaechol Lee, Songrim Jang, Doowhan Choi, Keunsoo Lee, Jumin Lee
  • Patent number: 11990407
    Abstract: A semiconductor device includes first and second wiring layers, and first and second via plugs. The first wiring layer has parallel tracks along which wirings are laid out, the tracks including first and second outer tracks and an inner track between the first and second outer tracks, the wirings including a first line laid out along the first outer track and having an end portion that is laid out along the first outer track, and a second line laid out along the inner track and having an end portion that is laid out along the first outer track. The first via plug is in contact with the end portion of the first line and extends between the first and second wiring layers, and the second via plug is in contact with the end portion of the second line and extends between the first and second wiring layers.
    Type: Grant
    Filed: November 17, 2022
    Date of Patent: May 21, 2024
    Assignee: Kioxia Corporation
    Inventors: Tomohiro Hasegawa, Kouji Nakao, Hiroshi Nasu
  • Patent number: 11985831
    Abstract: An apparatus and configuring scheme where a ferroelectric capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the ferroelectric capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and pull-down devices are turned on in a sequence, and inputs to the capacitors are set to condition the voltage on node n1. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: May 14, 2024
    Assignee: Kepler Computing Inc.
    Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni
  • Patent number: 11983479
    Abstract: A method of fabricating an integrated circuit includes placing a first set of conductive feature patterns on a first level, placing a second set of conductive feature patterns on a second level, placing a first set of via patterns between the second set of conductive feature patterns and the first set of conductive feature patterns, placing a third set of conductive feature patterns on a third level different from the first level and the second level, placing a second set of via patterns between the third set of conductive feature patterns and the second set of conductive feature patterns, and manufacturing the integrated circuit based on at least one of the above patterns of the integrated circuit.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Chan Yang, Ting-Wei Chiang, Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu, Li-Chun Tien, Meng-Hung Shen, Shang-Chih Hsieh, Chi-Yu Lu
  • Patent number: 11985853
    Abstract: A display panel and a display device are provided. The display panel includes a first display area and a second display area, wherein the display panel includes: a base substrate; a plurality of first repeating units arranged on the base substrate in an array and located in the first display area, each of the first repeating units including at least a first sub-pixel; a plurality of second repeating units arranged on the base substrate in an array and located in the second display area, each of the second repeating units including at least a second sub-pixel, wherein a color of light emitted by the first sub-pixel is the same as a color of light emitted by the second sub-pixel; a pixel defining layer disposed on the base substrate and located in both the first display area and the second display area, wherein the pixel defining layer includes a first opening located in the first display area and a second opening located in the second display area.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: May 14, 2024
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Youngyik Ko, Chi Yu, Wei Zhang, Yu Zhang, Weiyun Huang
  • Patent number: 11975963
    Abstract: A microelectromechanical systems (MEMS) device includes a MEMS die and an electrical circuit electrically connected to the MEMS die. The electrical circuit includes a first capacitor that produces a first output signal based on a signal received from the MEMS die, and a second capacitor that produces a second output signal based on a signal received from the MEMS die. The electrical circuit is configured to determine a nominal capacitance of the MEMS die based on a ratio of the first output signal to the second output signal and a ratio of the capacitances of the first and second capacitors.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: May 7, 2024
    Inventors: John J. Albers, Jorge Grilo
  • Patent number: 11978672
    Abstract: A semiconductor device includes a semiconductor substrate, a source/drain region, a source/drain contact and a conductive via and a first polymer layer. The source/drain region is in the semiconductor substrate. The source/drain contact is over the source/drain region. The conductive via is over the source/drain contact. From a top view, the conductive via has two opposite long sides and two opposite short sides connecting the long sides, and the short sides are shorter than the long sides and more curved than the long sides.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Chin Chang, Li-Te Lin, Pinyen Lin
  • Patent number: 11980037
    Abstract: Described herein are ferroelectric (FE) memory cells that include transistors having gate stacks separate from FE capacitors of these cells. An example memory cell may be implemented as an IC device that includes a support structure (e.g., a substrate) and a transistor provided over the support structure and including a gate stack. The IC device also includes a FE capacitor having a first capacitor electrode, a second capacitor electrode, and a capacitor insulator of a FE material between the first capacitor electrode and the second capacitor electrode, where the FE capacitor is separate from the gate stack (i.e., is not integrated within the gate stack and does not have any layers that are part of the gate stack). The IC device further includes an interconnect structure, configured to electrically couple the gate stack and the first capacitor electrode.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: May 7, 2024
    Assignee: Intel Corporation
    Inventors: Nazila Haratipour, Shriram Shivaraman, Sou-Chi Chang, Jack T. Kavalieros, Uygar E. Avci, Chia-Ching Lin, Seung Hoon Sung, Ashish Verma Penumatcha, Ian A. Young, Devin R. Merrill, Matthew V. Metz, I-Cheng Tung
  • Patent number: 11980069
    Abstract: A display includes a display substrate and a flexible circuit board. The display substrate includes a silicon substrate, a driving circuit of which at least part is embedded in the silicon substrate, and a first pad electrically connected with the driving circuit. The driving circuit includes a transistor with a semiconductor layer; the flexible circuit board includes a flexible substrate, a first wiring layer, and a first reinforcement plate. The first wiring layer includes a main wiring portion and a second pad electrically connected with the main wiring portion, and the second pad is electrically connected with the first pad by a conductive adhesive layer. The first reinforcement plate covers the main wiring portion and does not cover the second pad. The first reinforcement plate is located outside the display substrate and there is a non-zero distance between the first reinforcement plate and the display substrate.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: May 7, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiao Bai, Shengji Yang, Pengcheng Lu
  • Patent number: 11974462
    Abstract: Disclosed are a display panel and a display device. The display panel includes a base substrate; a plurality of data signal lines on the base substrate, and a plurality of pixel units; and each pixel unit has a transparent area and a non-transparent area; the pixel unit includes a plurality of sub-pixels in the non-transparent area. All sub-pixels in the display panel are arranged in an array, each column of sub-pixels corresponds to a respective one of the data signal lines, and at least part of the data signal lines are arranged around the transparent areas.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: April 30, 2024
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Ling Wang, Yicheng Lin, Pan Xu, Guoying Wang, Guang Yan
  • Patent number: 11973021
    Abstract: A semiconductor device includes a first metal layer, a second metal layer, and an inter-metal dielectric layer disposed between the first metal layer and the second metal layer. The inter-metal dielectric layer includes: a first dielectric layer disposed on the first metal layer and in direct contact with the first metal layer, wherein the first dielectric layer has a stress value less than 0; a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer has a stress value greater than 0; and a third dielectric layer disposed on the second dielectric layer, wherein the third dielectric layer has a stress value less than 0. A thickness of the third dielectric layer is greater than a thickness of the second dielectric layer, and the thickness of the second dielectric layer is greater than a thickness of the first dielectric layer.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: April 30, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Kai-Chun Chen, Shih-Ming Tseng, Hsing-Chao Liu, Hsiao-Ying Yang
  • Patent number: 11973093
    Abstract: A single photon avalanche (SPAD) device configured to detect visible to infrared light includes a substrate and a trench coupled to the substrate. The trench has a lattice mismatch with the substrate and has a height equal to or greater than its width. The device further includes a substantially defect-free semiconductor region that includes photosensitive material. The semiconductor region includes a well coupled to the trench and doped a first type. The well is configured to detect a photon and generate a current. The semiconductor region also includes a region formed in the well and doped a second type opposite to the first type. The well is configured to cause an avalanche multiplication of the current. The trench and the well form a first electrode and the region forms a second electrode.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: April 30, 2024
    Assignee: SEMIKING LLC
    Inventors: Clifford Alan King, Anders Ingvar Aberg
  • Patent number: 11972954
    Abstract: An alternating stack of first material layers and second material layers can be formed over a semiconductor material layer. A patterning film is formed over the alternating stack, and openings are formed through the patterning film. Via openings are formed through the alternating stack at least to a top surface of the semiconductor material layer by performing a first anisotropic etch process that transfers a pattern of the openings in the patterning film. A cladding liner can be formed on a top surface of the patterning film and sidewalls of the openings in the pattering film. The via openings can be vertically extended through the semiconductor material layer at least to a bottom surface of the semiconductor material layer by performing a second anisotropic etch process employing the cladding liner as an etch mask.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: April 30, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Roshan Jayakhar Tirukkonda, Senaka Kanakamedala, Rahul Sharangpani, Raghuveer S. Makala, Monica Titus
  • Patent number: 11963405
    Abstract: A display and a display panel are provided. An additional VDD wire is arranged in an irregular-shaped region. The VDD wire is connected to a pixel arranged in the irregular-shaped region through a plurality of connection wires, such that the display may have a narrow side edge, and at the same time, a difference between impedances of the irregular-shaped region and a regular-shaped display region may not be large, and a display region may not be split.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: April 16, 2024
    Assignee: KunShan Go-Visionox Opto-Electronics Co., Ltd.
    Inventors: Miao Chang, Weilong Li, Lu Zhang, Siming Hu, Zhenzhen Han
  • Patent number: 11963397
    Abstract: A display region includes a plurality of pixel driving circuitry setting regions arranged sequentially in a first direction, and each pixel driving circuitry setting region extends in a second direction intersecting the first direction. Each display circuitry includes a plurality of subpixels in one-to-one correspondence with the pixel driving circuitry setting regions, each subpixel includes a subpixel driving circuitry and a light-emitting element coupled to each other, the subpixel driving circuitry is located in a corresponding pixel driving circuitry setting region, the light-emitting element is located at a side of the subpixel driving circuitry away from the substrate, a width of the light-emitting element is greater than a width of the corresponding pixel driving circuitry setting region in the first direction, and a length of the light-emitting element is smaller than a length of the corresponding pixel driving circuitry setting region in the second direction.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: April 16, 2024
    Assignees: HEFEI BOE JOINT TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Meng Li, Yongqian Li, Jingquan Wang, Chen Xu, Dacheng Zhang, Zhidong Yuan, Can Yuan, Xuehuan Feng
  • Patent number: 11956975
    Abstract: Structures and methods are provided for integrating a resistance random access memory (ReRAM) in a back-end-on-the-line (BEOL) fat wire level. In one embodiment, a ReRAM device area contact structure is provided in the BEOL fat wire level that has at least a lower via portion that contacts a surface of a top electrode of a ReRAM device area ReRAM-containing stack. In other embodiments, a tall ReRAM device area bottom electrode is provided in the BEOL fat wire level and embedded in a dielectric material stack that includes a dielectric capping layer and an interlayer dielectric material layer.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: April 9, 2024
    Assignee: International Business Machines Corporation
    Inventors: Soon-Cheon Seo, Dexin Kong, Takashi Ando, Paul Charles Jamison, Hiroyuki Miyazoe, Youngseok Kim, Nicole Saulnier, Vijay Narayanan, Iqbal Rashid Saraf
  • Patent number: 11948944
    Abstract: Stacked FET devices having wrap-around contacts to optimize contact resistance and techniques for formation thereof are provided. In one aspect, a stacked FET device includes: a bottom-level FET(s) on a substrate; lower contact vias present in an ILD disposed over the bottom-level FET(s); a top-level FET(s) present over the lower contact vias; and top-level FET source/drain contacts that wrap-around source/drain regions of the top-level FET(s), wherein the lower contact vias connect the top-level FET source/drain contacts to source/drain regions of the bottom-level FET(s). When not vertically aligned, a local interconnect can be used to connect a given one of the lower contact vias to a given one of the top-level FET source/drain contacts. A method of forming a stacked FET device is also provided.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: April 2, 2024
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Heng Wu, Jingyun Zhang, Julien Frougier
  • Patent number: 11950432
    Abstract: A semiconductor package includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first semiconductor substrate, a first bonding structure and a memory cell. The second semiconductor device is stacked over the first semiconductor device. The second semiconductor device includes a second semiconductor substrate, a second bonding structure in a second dielectric layer and a peripheral circuit between the second semiconductor substrate and the second bonding structure. The first bonding structure and the second bonding structure are bonded and disposed between the memory cell and the peripheral circuit, and the memory cell and the peripheral circuit are electrically connected through the first bonding structure and the second bonding structure.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Ku Shen, Ku-Feng Lin, Liang-Wei Wang, Dian-Hau Chen