Patents Examined by Tuan T. Lam
  • Patent number: 10380935
    Abstract: The present disclosure provides a gate driving circuit, a gate driving method and a display method. The gate driving circuit includes a pull-up node control circuitry, a pull-down node control circuitry, a display storage circuitry, a compensation storage circuitry and a compensation storage control circuitry. The compensation storage control circuitry is connected to an input terminal, a pull-down control voltage terminal, a pull-up node, a pull-down node, and a second terminal of the compensation storage circuitry, and configured to enable the pull-down control voltage terminal to be electrically connected to the second terminal of the compensation storage circuitry under the control of the input terminal so as to charge the compensation storage circuitry, and enable the second terminal of the compensation storage circuitry to be electrically connected to the pull-up node.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: August 13, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Liqing Liao, Hongmin Li, Ping Song
  • Patent number: 10373562
    Abstract: The present application provides a gate driver circuit comprising at least one cascaded gate driver circuit unit. The low-level-holding enabling terminal of the gate driver circuit unit is connected to an adaptive voltage generating module. The adaptive voltage generating module generates a self-compensating voltage according to its constant current source and transmits to the low-level-holding enabling terminal, so as to provide an effective voltage level to the low-level-holding enabling terminal. Because the threshold voltage shift caused by pulling-down transistors in the low-level-holding module is embodied at the low-level-holding enabling terminal, the adaptive voltage generating module generates a self-compensating voltage with its constant current source according to the threshold voltage to compensate the increase of the threshold voltage.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: August 6, 2019
    Assignee: Peking University Shenzhen Graduate School
    Inventors: Shengdong Zhang, Chuanli Leng, Zhijin Hu, Congwei Liao
  • Patent number: 10360834
    Abstract: A display substrate includes a first substrate having a display area and a non-display area, a plurality of pixels at the display area, and a gate driving circuit at the non-display area and including an output transistor including a channel region, an insulation layer covering the output transistor, and a capacitor on the insulation layer, electrically connected to the output transistor, and including a first capacitor electrode on the insulation layer, overlapping the channel region of the output transistor, and electrically connected to a first electrode of the output transistor, a first protection layer covering the first capacitor electrode, and a second capacitor electrode on the first protection layer, overlapping the channel region of the output transistor, and electrically connected to a gate electrode of the output transistor.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: July 23, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Wonho Kim, Sungman Kim, Hyeonhwan Kim, Seongsu Lim, Sangjin Jeon
  • Patent number: 10340021
    Abstract: An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: July 2, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Seiko Amano, Kouhei Toyotaka, Hiroyuki Miyake, Aya Miyazaki, Hideaki Shishido, Koji Kusunoki
  • Patent number: 10332444
    Abstract: A shift register unit is disclosed, including a first input module transmitting a first level voltage signal to a first node under control of a voltage signal of a second node; a reset module transmitting a second level voltage signal to the first node under control of an output signal of the present stage of shift register unit; a first output module outputting the second level voltage signal to the output terminal of the shift register unit under control of a voltage signal of the first node; a second input module receiving an input signal and transmitting the input signal to the second node under control of a clock signal; a storage capacitor maintaining the voltage of the second node while the second input module is turned off; and a second output module outputting the first level voltage signal to the output terminal.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: June 25, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Zhanjie Ma
  • Patent number: 10325932
    Abstract: An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: June 18, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Umezaki
  • Patent number: 10319283
    Abstract: Provided are a gate driving circuit and a display device including the same. The gate driving circuit according to an embodiment includes a shift register including a plurality of stages. An nth stage of the stages includes a latch control circuit including a first NMOS transistor connected to a QB node, a second NMOS transistor connected to a Q node, and a third NMOS transistor having a gate electrode to which a first clock is input and connected to the first and second NMOS transistors, where n is a positive integer. A latch is connected between the Q and QB nodes. A transmission gate is connected to the Q and QB nodes. In the gate driving circuit, output signals of a previous stage and a following stage are controlled so as to be synchronized with the first clock to suppress a glitch.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: June 11, 2019
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Byungil Kim, Seokhwan Choi
  • Patent number: 10297332
    Abstract: A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: May 21, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Umezaki
  • Patent number: 10298023
    Abstract: A power supply includes an LLC resonant power converter to provide a first reference signal having a first voltage. The power supply also includes a DC-DC power converter to provide a second reference signal having a second voltage. The DC-DC converter receives power from the first reference signal. The power supply further includes a switch circuit including a first input to receive the first reference signal, a second input to receive the second reference signal, an input to receive a switch control message, and an output coupled to a power rail. The switch circuit is configured to connect the first reference signal and the second reference signal to the power rail based on the switch control message.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: May 21, 2019
    Assignee: Dell Products, LP
    Inventors: Tsung-Cheng Anson Liao, Wei-Cheng Jason Yu, Yang Wang, Tso-Jen Hunter Peng
  • Patent number: 10297331
    Abstract: A highly reliable semiconductor device is provided. A semiconductor device includes a shift register including a pulse output circuit formed using transistors having the same conductivity type, or the like. A transistor including a back gate is used as a transistor in which a potential difference between a source and a drain is not generated and positive stress is applied to a gate in a non-selection period of the pulse output circuit. In the non-selection period, stress applied to the transistors is reduced by interchanging the potentials of the gates and those of the back gates.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: May 21, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hiroyuki Miyake
  • Patent number: 10283211
    Abstract: Disclosed are a shift register unit and a driving method thereof, a shift register and a display device. The shift register unit comprises: an input module (P1), which connected to a first clock signal end (Clk1), a second clock signal end (Clk2) and a data carry signal end (STV) and is used for providing a selection signal according to signals input via the first clock signal end (Clk1), the second clock signal end (Clk2) and the data carry signal end (STV); and an output module (P2), which is connected to a high level end (VGH), a low level end (VGL), and an output end (Output) of the shift register unit and is used for selectively outputting a high level or a low level at the output end (Output) according to the selection signal provided by the input module (P1). The shift register comprises a plurality of stages of shift register units, and the display device comprises a shift register.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: May 7, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Zhanjie Ma
  • Patent number: 10283038
    Abstract: A shift register unit and a method for driving the shift register unit, a gate drive circuit and a display device are provided. The shift register unit includes a driving signal generating module and a selecting module. The driving signal generating module generates a driving signal for driving n rows of gate lines to be turned on, a duration of the driving signal being equal to a duration spent on scanning the n rows of gate lines, and n is equal to or greater than 2. The selecting module, connected to the driving signal generating module and input terminals of the n rows of gate lines, selects the n rows of gate lines sequentially and connects each selected gate line to the driving signal generating module, such that the driving signal is inputted to the n rows of gate lines sequentially.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: May 7, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD, HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xiaoliang Zhou, Hongwei Wang, Fei Yu, Lei Jiang
  • Patent number: 10283039
    Abstract: The present application discloses an N-th shift register unit circuit including at least a gate-drive signal output sub-circuit, a pull-up control sub-circuit, and a pull-down control sub-circuit respectively connected between a pull-up node and a pull-down node and provided with a p-th clock signal in addition to an n-th clock signal. A driving method includes controlling the pull-down node at turn-off voltage level when the p-th clock signal is at turn-on voltage level during which the n-th clock signal is correspondingly rising to turn-on voltage level from turn-off voltage level.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: May 7, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hyunsic Choi, Seungwoo Han
  • Patent number: 10276254
    Abstract: The present disclosure describes a shift register unit, an organic light-emitting display panel and a driving method. The shift register unit comprises a node potential controller and an output unit. The node potential controller comprises a first output end and a second output end. The output unit is configured to output, based on a first control signal from the first output end and a second control signal from the second output end, a first level signal or a second level signal. According to the solutions provided by the application, the potential of each node in the shift register unit is stable and controllable, and contributed to the avoidance of output logic execution problem in the shift register unit caused by unstable node potential when each control signal level of the shift register unit jumps.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: April 30, 2019
    Assignees: SHANGHAI TIANMA AM-OLED CO., LTD., TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Dongxu Xiang, Yue Li, Dong Qian, Gang Liu
  • Patent number: 10276119
    Abstract: An output control node stabilization portion includes a thin film transistor having a gate terminal to which is provided a fourth clock that changes to an on level at timing at which a scanning signal outputted from a previous stage is to change from an off level to an on level, a drain terminal connected to an output control node, and a source terminal to which the scanning signal outputted from the previous stage is provided; and a thin film transistor having a gate terminal to which is provided a third clock that changes to an on level at timing at which a scanning signal outputted from a subsequent stage is to change from an off level to an on level, a drain terminal connected to the output control node, and a source terminal to which the scanning signal outputted from the subsequent stage is provided.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: April 30, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Toshitsugu Sueki, Yasuaki Iwase, Takuya Watanabe, Akira Tagawa, Kengo Hara
  • Patent number: 10276122
    Abstract: In a forward shift operation, a second input signal having a higher voltage than a voltage of a first input signal is input to a second gate terminal in a case that a first gate terminal of a first transistor is charged, and a fourth input signal having a higher voltage than a voltage of a third input signal is input to a third gate terminal in a case that the first gate terminal of the first transistor is discharged. In a backward shift operation, the fourth input signal having a higher voltage than a voltage of the third input signal is input to the third gate terminal in a case that the first gate terminal of the first transistor is charged, and the second input signal having a higher voltage than a voltage of the first input signal is input to the second gate terminal in a case that the first gate terminal of the first transistor is discharged.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: April 30, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kaoru Yamamoto, Yasuyuki Ogawa
  • Patent number: 10268306
    Abstract: A shift register unit is provided. The shift register unit includes a precharging module, a resetting module, a pull-up control module and a noise reduction module. The precharging module is connected to the resetting module and a pull-up node, the resetting module is connected to the pull-up node, the noise reduction module and an output end, the pull-up control module is connected to the pull-up node, the noise reduction module and the output end, and the noise output module is connected to the output end.
    Type: Grant
    Filed: October 9, 2016
    Date of Patent: April 23, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Honggang Gu, Xianjie Shao, Xiaohe Li, Zhangmeng Wang, Jie Song
  • Patent number: 10269289
    Abstract: A shift register includes a control circuit, a switching circuit, a driving circuit, and a pull-down circuit. The control circuit is configured to output a control signal having a high level during a pull-up period and a voltage-regulating period respectively. The switching circuit is configured to provide a control voltage according to the control signal and a front stage signal outputted by a front x-stage shift register during the pull-up period. The driving circuit is configured to generate a driving signal according to the control voltage provided by the switching circuit, and output a home stage scan signal based on the driving signal. The pull-down circuit is configured to pull down a voltage level of the driving signal according to a scan signal outputted by a rear y-stage shift register during a pull-down period. The switching circuit is configured to regulate the driving signal and the home stage scan signal.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: April 23, 2019
    Assignee: AU OPTRONICS CORP.
    Inventors: Wei-Li Lin, Che-Wei Tung, Yan-Ting Chen
  • Patent number: 10262617
    Abstract: The present invention is related to a gate driving circuit for a display device. The gate driving circuit may comprise x stages of driving shift register units connected in series. Each of the driving shift register units may comprise an input terminal, an output terminal, and a reset terminal. The input terminal may comprise a first input port and a second input port. A row of pixel units driven by the driving shift register unit of the m-th stage may have the same polarity distribution as a row of pixel units driven by the driving shift register unit of the (m?N)-th stage. N is an integer greater than 1. m is an integer and N+1<m?x.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: April 16, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., Hefei Xinsheng Optoelectronics Technology Co., Ltd.
    Inventors: Jian Zhao, Hui Wang
  • Patent number: 10262749
    Abstract: A shift register unit comprises a pull-up module, a clock signal input terminal, a storage module, a signal output terminal, a control voltage signal input terminal and a current leakage suppression module. An output terminal of the current leakage suppression module is connected to a control terminal of the pull-up module A first input terminal of the current leakage suppression module is connected to the control voltage signal input terminal A second input terminal of the current leakage suppression module is connected to the other end of the storage module. A driving method uses a shift register unit, a shift register, a gate driving circuit, and a display device.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: April 16, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Bin Feng, Junwei Wang, Ming Tian