Patents Examined by Tuan T. Lam
-
Patent number: 11929129Abstract: In one implementation, a circuit includes: a comparator; a shift register chain coupled to the comparator; and one or more converters coupled to respective shift registers of the shift register chain, wherein the one or more converters are configured to convert a source of current from a first voltage to a second voltage, and wherein the circuit is configured to selectively transmit an output signal to the one or more converters. In one implementation, the circuit is configured to selectively control modulation for the one or more converters.Type: GrantFiled: January 26, 2022Date of Patent: March 12, 2024Assignee: Arm LimitedInventor: David Victor Pietromonaco
-
Patent number: 11927635Abstract: A charge pump test configuration and corresponding method of operation are disclosed for determining charge pump efficiency without needing to obtain direct current measurements. A first number of clock edges (CEs) of a clock signal supplied to a first charge pump is determined over a period of time for a predetermined output current. The first charge pump is then connected with a charge pump under test (PUT) in a cascaded manner such that an output current of the first charge pump is supplied to the PUT as an input current. A second number of CEs of a clock signal supplied to the first charge pump is determined over the same period of time for the same predetermined output current from the PUT. The efficiency of the PUT can then be determined as the ratio of the first number of CEs to the second number of CEs, or vice versa.Type: GrantFiled: April 28, 2022Date of Patent: March 12, 2024Assignee: SANDISK TECHNOLOGIES LLCInventors: Keyur Payak, Naveen Thomas
-
Patent number: 11923835Abstract: A driving module including a voltage mode driver and a current mode driver is provided. The voltage mode driver converts a positive input signal to a positive output signal at a positive output terminal, and converts a negative input signal to a negative output signal at a negative output terminal. The current mode driver includes a first current source, a second current source, and a third current source. The first current source provides a first current to one of the positive output terminal and the negative output terminal. The second current source provides a second current to one of the positive output terminal and the negative output terminal. The third current source provides a third current to one of the positive output terminal and the negative output terminal.Type: GrantFiled: June 20, 2022Date of Patent: March 5, 2024Assignee: KEY ASIC INC.Inventor: Shahbaz Abbasi
-
Patent number: 11923855Abstract: An integrated circuit includes an input pad and a Schmitt trigger coupled to the input pad. The Schmitt trigger includes a first inverter and a second inverter. The Schmitt trigger includes a pull-up transistor coupled to an input of the second inverter and configure to supply a high reference voltage to the input of the second inverter.Type: GrantFiled: September 13, 2022Date of Patent: March 5, 2024Assignee: STMicroelectronics International N.V.Inventors: Manoj Kumar Tiwari, Saiyid Mohammad Irshad Rizvi
-
Patent number: 11923849Abstract: A frequency divider is provided that includes a plurality of latches for dividing an input clock according to an integer frequency divisor N of three or greater. Each latch is coupled to a corresponding pair of logic gates. For each latch, one of the logic gates in the corresponding pair controls a setting of the latch whereas a remaining one of the logic gates in the corresponding pair controls a resetting of the latch. Each latch outputs a pair of overlapping clock signals that are divided in frequency with respect to the input clock and have a 50% duty cycle. Each logic gate processes a pair of the overlapping clock signal and the input clock signal to provide a non-overlapping clock signal of the same frequency of the overlapping clock signals but have a (50/N) % duty cycle.Type: GrantFiled: August 30, 2022Date of Patent: March 5, 2024Assignee: QUALCOMM INCORPORATEDInventor: Nagarjuna Nallam
-
Patent number: 11923856Abstract: Methods and apparatus for time-to-digital conversion. An example apparatus includes a first input; a second input; a delay line coupled to the first input and comprising a plurality of first delay elements coupled in series, each of the plurality of first delay elements having a first delay time; a second delay element having an input coupled to the second input and having the first delay time; a third delay element having an input coupled to the second input and having a second delay time, the second delay time being smaller than the first delay time; a first set of arbiters having first inputs coupled to the delay line and having second inputs coupled to an output of the second delay element; and a second set of arbiters having first inputs coupled to the delay line and having second inputs coupled to an output of the third delay element.Type: GrantFiled: April 5, 2022Date of Patent: March 5, 2024Assignee: XILINX, INC.Inventors: Bob W. Verbruggen, Christophe Erdmann
-
Patent number: 11923850Abstract: A motor control system includes a DC motor and a ripple count circuit. The DC motor includes a rotor that rotates in response to a drive current. The rotation of the rotor generates a mechanical force that drives a component. The ripple count circuit includes an active filter circuit and a parasitic pulse cancellation circuit. The active filter circuit is configured to filter the drive current and to generate a pulsed signal. The parasitic pulse cancelation circuit is in signal communication with the ripple count circuit to receive the pulsed signal and generates a ripple count signal that excludes parasitic pulses included in the pulsed signal having a parasitic voltage level that exceeds a voltage level of a voltage threshold. The parasitic pulse cancelation circuit actively adjusts the voltage level of the voltage threshold based at least in part on a rotational direction of the rotor.Type: GrantFiled: April 7, 2022Date of Patent: March 5, 2024Assignee: INTEVA PRODUCTS, LLCInventor: François Breynaert
-
Patent number: 11916547Abstract: A semiconductor relay device includes a conversion circuit configured to receive an input signal from outside and pass a first current to a first node based on the input signal. A zener diode has an anode coupled to a second node and a cathode coupled to the first node. A resistor is coupled between the second node and a third node. A number n of diodes are serially coupled. A thyristor has an anode coupled to the first node, a cathode coupled to the second node, and a control terminal coupled to the third node. A transistor has a gate coupled to the first node. An anode of a diode at a first end of the n diodes is coupled to the first node, and a cathode of a diode at a second end of the n diodes is coupled to a third node.Type: GrantFiled: September 2, 2022Date of Patent: February 27, 2024Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Naoya Takai, Yukihiro Takifuji, Keita Saito, Kazuki Tanaka
-
Patent number: 11916554Abstract: Examples may include techniques for using a sample clock to measure a duty cycle by periodic sampling a target clock signal based on a prime number ratio of a reference clock frequency. The reference clock frequency used to set a measurement cycle time over which the duty cycle is to be measured. A magnitude of a duty cycle error as compared to a programmable target duty cycle is determined based on the measured duty cycle and the duty cycle is adjusted based, at least in part, on the magnitude of the duty cycle error.Type: GrantFiled: December 16, 2019Date of Patent: February 27, 2024Assignee: Intel CorporationInventors: Christopher P. Mozak, Ralph S. Li, Chin Wah Lim, Mahmoud Elassal, Anant Balakrishnan, Isaac Ali
-
Patent number: 11908417Abstract: A gate driving circuit including a controller for providing a first carry signal to a control node, a first pull-up portion for outputting a first clock signal as a first gate signal in accordance with a signal provided to the control node, and a second pull-up portion for outputting a second clock signal with a phase that is different from the first clock signal as a second gate signal in accordance with the signal provided to the control node.Type: GrantFiled: April 25, 2022Date of Patent: February 20, 2024Assignee: Samsung Display Co., Ltd.Inventors: Kang Nam Kim, You Mee Hyun, Beom Jun Kim, Jong Hwan Lee, Sung Hoon Lim, Duc Han Cho
-
Patent number: 11909402Abstract: Devices and methods are described herein for a pulse amplitude modulation (PAM) driver. In one embodiment, the PAM driver includes a first high-speed buffer configured to output a first voltage, a second high-speed buffer configured to output a second voltage, and a plurality of transistors coupled to the first high-speed buffer and the second high-speed buffer. At least one of the first voltage or the second voltage facilitates selective operation of a transistor of the plurality of transistors to output a third voltage.Type: GrantFiled: June 23, 2022Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Paul Ranucci, Alan Roth
-
Patent number: 11904756Abstract: A method for controlling a headlamp of a motor vehicle, the headlamp comprising a plurality of light sources. A projection symbol to be projected by the headlamp and a position and a size of the projection symbol are determined. A respective first luminous intensity for the light sources for the projection of the projection symbol at the position with the size and a first indicator, which contains an indication of how greatly the individual first luminous intensities differ from one another are determined. The position and/or the size of the projection symbol is changed. A respective second luminous intensity for the light sources for the projection of the projection symbol at the changed position and/or with the changed size and a second indicator, which contains an indication of how greatly the individual second luminous intensities differ from one another are determined. The projection symbol subsequently projected.Type: GrantFiled: October 29, 2021Date of Patent: February 20, 2024Assignee: Hella GmbH & Co. KGaAInventors: Christian Huester, Boris Kubitza, Martin Pluempe, Udo Venker, Carsten Wilks
-
Patent number: 11909401Abstract: An input driven self-clocked dynamic comparator, and associated systems and methods are described herein. In one embodiment, self-clocked dynamic comparator, includes a latch configured to receive an input voltage (VIN), a reference voltage (VREF) and a clocking (CLKsf) signal, and configured to output a first rail-to-rail output (OUT+) signal and a second rail-to-rail output (OUT?) signal. The self-clocked dynamic comparator also includes a pre-amplifier (PRE-AMP) configured to output an enable (TRI) signal based on a comparison between the VIN and an adjusted VREF. The self-clocked dynamic comparator further includes a pre-amplifier (PRE-AMP) configured to output an enable (TRI) signal based on a comparison between the VIN and an adjusted VREF, and a logic gate configured to receive the TRI signal and one of the OUT+ signal and OUT? signal, and configured to output the CLKsf signal. The cycles of the CLKsf signal cause the latch to dissipate energy.Type: GrantFiled: October 9, 2020Date of Patent: February 20, 2024Assignee: University of WashingtonInventors: Samrat Dey, Thomas Lewellen, Jacques Christophe Rudell
-
Patent number: 11901900Abstract: An integrated circuit includes an input pad and a Schmitt trigger coupled to the input pad. The Schmitt trigger includes a main PMOS branch that charges an intermediate node of the Schmitt trigger responsive to voltage transitions at the input node. The Schmitt trigger includes a charging assistance circuit that helps to rapidly charge the intermediate node of the Schmitt trigger. The charging assistance circuit includes a parallel PMOS branch in parallel with the main PMOS branch.Type: GrantFiled: June 17, 2022Date of Patent: February 13, 2024Assignee: STMicroelectronics International N.V.Inventors: Kailash Kumar, Manoj Kumar
-
Patent number: 11894849Abstract: The present invention provides a Schmitt trigger circuit in which chattering does not occur in the output of the Schmitt trigger circuit even when it is connected to a communication bus without impedance matching and reflected noise is superimposed on the input signal. The Schmitt trigger circuit includes: a first signal detection circuit; a second signal detection circuit; a latch circuit; a selection signal generation circuit; a first input port; and a first output port. The first signal detection circuit is connected to the first input port, the latch circuit and the selection signal generation circuit. The second signal detection circuit is connected to the first input port, the latch circuit and the selection signal generation circuit. The latch circuit is connected to the selection signal generation circuit and the output port. The selection signal generation circuit includes a delay circuit.Type: GrantFiled: October 14, 2022Date of Patent: February 6, 2024Assignee: ABLIC Inc.Inventors: Junichi Kanno, Yasushi Imai
-
Patent number: 11888482Abstract: A system comprises a first comparator, a second comparator, a pulse-width modulation (PWM) controller, and a ramp generator. The first comparator has a positive input coupled to a first ramp output of the ramp generator and a negative input configured to receive an input voltage. The second comparator has a positive input configured to receive the input voltage and a negative input coupled to a second ramp output of the ramp generator. The PWM controller is coupled to outputs and control signal inputs of the first and second comparators and has a control output. In some implementations, the ramp generator generates a high-side falling ramp for the first comparator and a low-side rising ramp for the second comparator. In some implementations, the ramp generator includes a first ramp generator for the high-side falling ramp and a second ramp for the low-side rising ramp.Type: GrantFiled: December 29, 2021Date of Patent: January 30, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Chen Jiang, Shamim Choudhury, Subrahmanya Bharathi Akondy
-
Patent number: 11881859Abstract: A circuit includes an inverter coupled between an input and an output. The inverter includes first and second pull-down transistors having control terminals coupled to the input, a pull-up resistor, and a pull-up transistor having a control terminal coupled to the input. The first and second pull-down transistors are coupled in series along a pull-down path extending between a first voltage supply terminal and the output. The pull-up resistor and pull-up transistor are coupled in series along a pull-up path extending between a second voltage supply terminal and the output. A hysteresis transistor has a control terminal coupled to the output. The hysteresis transistor is coupled to the inverter along a hysteresis path extending between the first voltage supply terminal and the pull-up path. A clamp circuit is coupled to the inverter along a clamp path extending between the first voltage supply terminal and the pull-down path.Type: GrantFiled: May 20, 2022Date of Patent: January 23, 2024Assignee: Texas Instruments IncorporatedInventors: Abhishek Gupta, Sayantan Gupta
-
Patent number: 11881830Abstract: A filter circuit includes multiple registers, a switch circuit, multiple multipliers and a summation circuit. Each register is configured to store an input. The switch circuit is coupled to the registers and configured to receive the inputs from the registers as a series of registered inputs and adjust arrangement of the inputs of the series of registered inputs to generate a series of rearranged inputs according to a count value. The count value is accumulated in response to reception of a new input of the filter circuit. The multipliers are coupled to the switch circuit. The inputs of the series of rearranged inputs are sequentially provided to the multipliers. Each multiplier is configured to generate a multiplication result according to the received input and a coefficient. The summation circuit is coupled to the multipliers and configured to sum up the multiplication results to generate an output.Type: GrantFiled: February 7, 2021Date of Patent: January 23, 2024Assignee: Realtek Semiconductor Corp.Inventor: Chih-Hao Liu
-
Patent number: 11876352Abstract: The present invention concerns a device for pulsed electric discharge in a liquid comprising a control module configured to control a voltage generator such that the voltage generator applies a predetermined heating voltage setpoint between electrodes during a heating period until a pulsed electric discharge is obtained between the electrodes, in order to measure the breakdown voltage during the pulsed electric discharge, in order to estimate the quantity of energy supplied to the liquid during the heating period, referred to as the “quantity of heating energy”, from the predetermined heating voltage setpoint and the measured breakdown voltage, and in order to determine a new heating voltage setpoint to apply between the electrodes of the at least one pair of electrodes at the next pulsed electric discharge based on the estimated quantity of heating energy and a predefined breakdown voltage setpoint.Type: GrantFiled: December 17, 2019Date of Patent: January 16, 2024Assignee: ADM28 FRANCEInventor: Romain Pecquois
-
Patent number: 11875972Abstract: Methods and devices for generating a voltage waveform at an output may include providing four DC voltages of different magnitudes. The first (V1) magnitude is higher than the third (V3) and fourth (V4) magnitude. The fourth DC voltage is coupled to the output followed by coupling the first DC voltage to the output, to bring an output voltage (VP) at the output to a high level. The first DC voltage is decoupled from the output, followed by coupling the third DC voltage to the output, to obtain a drop of the output voltage (VP). A ground potential (V0) is coupled to the output following coupling the third DC voltage and the second DC current (I2) is coupled to the output following coupling the ground potential, wherein the second DC current ramps down the output voltage (VP).Type: GrantFiled: April 21, 2020Date of Patent: January 16, 2024Assignee: PRODRIVE TECHNOLOGIES INNOVATION SERVICES B.V.Inventor: Antonius Wilhelmus Hendricus Johannes Driessen