Abstract: Stacked superconducting integrated circuits with three dimensional resonant clock networks are described. An apparatus, including a first superconducting integrated circuit having a first clock distribution network for distributing a first clock signal in the first superconducting integrated circuit, is provided. The apparatus further includes a second superconducting integrated circuit, stacked on top of the first superconducting integrated circuit, having a second clock distribution network for distributing a second clock signal in the second superconducting integrated circuit, where each of the first clock distribution network and the second clock distribution network comprises a clock structure having a plurality of unit cells, where each of the plurality of unit cells includes at least one spine and at least one stub, the at least one stub inductively coupled to a first superconducting circuit, and where each of the first clock signal and the second clock signal has a same resonant frequency.

Abstract: A flip-flop includes a first master latch in a first row, a second master latch in a second row, a first slave latch in the first row, and a second slave latch in the second row. The first master latch and the second master latch are adjacently disposed in the second direction, and the first slave latch and the second slave latch are adjacently disposed in the second direction.

Abstract: A clock signal delay path unit includes a first delay cell including a first root signal line for delaying and transmitting a clock signal, a first repeater to transmit the clock signal transmitted through the first root signal line without signal attenuation, and a second root signal line for delaying and transmitting the clock signal output from the first repeater, a second delay cell including a first inverting circuit configured to invert the clock signal provided from the first delay cell to generate an inverted clock signal, and a third delay cell including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater to transmit the inverted clock signal transmitted through the first branch signal line, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater.

Abstract: A compact RF switch with improved isolation is presented. According to one aspect, the RF switch includes a basic single-pole single-throw (SPST) switch element that includes an inductor in parallel with a series FET transistor. An inductance of the inductor is selected to provide in combination with an off capacitance of the series FET transistor a resonance at a specific frequency of interest. The frequency of interest can be in-band or out-of-band, including the band's fundamental frequency or a harmonic thereof. According to another aspect, the inductor is conditionally coupled to the series FET transistor via a reduced size FET transistor. Complex RF switches can include a plurality of the SPST switch elements, each tuned to a same or different frequency of interest. According to yet another aspect, SPST switch elements in their OFF states can provide matching to an SPST element in the ON state.

Abstract: A clock detecting circuit is provided. The clock detecting circuit includes a first clock converting circuit, a second clock converting circuit and a frequency comparator. The first clock converting circuit converts an internal clock to a first clock. The second clock converting circuit converts an external clock to a second clock. The frequency comparator generates a first edge clock in response the first clock and generates a second edge clock in response the second clock. The frequency comparator generates a first sensing voltage in response to a plurality of positive pulses of the first edge clock and generate a second sensing voltage in response to a plurality of positive pulses of the second edge clock. The frequency comparator compares the first sensing voltage and the second sensing voltage to provide a frequency comparing result between the external clock and the internal clock.

Abstract: To provide a novel shift register. Transistors 101 to 104 are provided. A first terminal of the transistor 101 is connected to a wiring 111 and a second terminal of the transistor 101 is connected to a wiring 112. A first terminal of the transistor 102 is connected to a wiring 113 and a second terminal of the transistor 102 is connected to the wiring 112. A first terminal of the transistor 103 is connected to the wiring 113 and a gate of the transistor 103 is connected to the wiring 111 or a wiring 119. A first terminal of the transistor 104 is connected to a second terminal of the transistor 103, a second terminal of the transistor 104 is connected to a gate of the transistor 101, and a gate of the transistor 104 is connected to a gate of the transistor 102.

Abstract: The invention relates to a phase sequencing three-phase network comprising a first side connected to a second side via the network. The first side comprises one endpoint (EP1) and the second side comprises three endpoints (EP2, EP3, and EP4). The network comprises five nodes (NP1-NP5) interconnected via feed line sections (FP1-FP10) comprising at least one transmission line section (R11-R102) each. The invention further relates to an optimization method for the network for deciding characteristic impedance and length of each transmission line section (R11-R102).

Abstract: In an embodiment an isolated gate driver device includes a low-voltage section having a control input configured to receive a PWM control signal with a switching frequency from a control stage, a high-voltage section, galvanically isolated from the low-voltage section the high-voltage section including a driving output configured to provide a gate-driving signal as a function of the PWM control signal to a power stage having at least one switch, a feedback input configured to receive at least one feedback signal indicative of an operation of the power stag, and an ADC module configured to convert the feedback signal into a digital data stream and a conversion-control module coupled to the ADC module and configured to provide a conversion-trigger signal designed to determine a start of a conversion for acquiring a new sample of the feedback signal.

Abstract: An adaptive anti-aging sensor based on a cuckoo algorithm, comprising a control module, a reference voltage-controlled oscillator, two shaping circuits, a frequency difference circuit, a resolution adjustment circuit, a 16-bit counter, a parallel-to-serial circuit, an adaptive module, and a digital-to-analog converter. A lookup table is prestored in the adaptive module; when aging monitoring is performed on a voltage-controlled oscillator in an integrated circuit, the adaptive module uses the cuckoo algorithm to determines the optimal working voltage of the currently monitored voltage-controlled oscillator, and the control module accordingly changes the input voltage of the voltage-controlled oscillator of the integrated circuit.

Abstract: This application provides a gallium nitride component and a drive circuit thereof. The gallium nitride component includes: a substrate; a gallium nitride (GaN) buffer layer formed on the substrate; an aluminum gallium nitride (AlGaN) barrier layer formed on the GaN buffer layer; and a source, a drain, and a gate formed on the AlGaN barrier layer. The gate includes a P-doped gallium nitride (P—GaN) cap layer formed on the AlGaN barrier layer, and a first gate metal and a second gate metal formed on the P—GaN cap layer. A Schottky contact is formed between the first gate metal and the P—GaN cap layer, and an ohmic contact is formed between the second gate metal and the P—GaN cap layer. In the technical solution provided in this application, the gallium nitride component is a normally-off component, and is conducive to design of a drive circuit.

Abstract: A microcontroller is coupled to a detection circuit which generates a detection signal. The microcontroller includes a processing circuit and an input-output circuit. The processing circuit generates an output signal according to the detection signal. In response to the output signal being at a specific level, the processing circuit enables a reset signal. The input-output circuit includes a latch circuit and a counter circuit. The latch circuit latches the output signal to generate a latched signal. The counter circuit starts adjusting the count value in response to the reset signal being enabled. The counter circuit changes the level of the latched signal in response to the count value being equal to a predetermined value.

Abstract: A bi-directional Gray code counter includes a first set of logic circuitry configured to receive an input having a first sequence of bits representing a first value. The first set of logic circuitry is further configured to convert the first sequence of bits to a second sequence of bits representing the first value. The bi-directional Gray code counter further includes a second set of logic circuitry and third second set of logic circuitry. The second set of logic circuitry is configured to compare the second sequence of bits to a bit index pattern. The third set of logic circuitry is configured to transition one bit in the first sequence of bits from a first state to a second state to form a third sequence of bits representing a second value. The one bit is transitioned in response to the second sequence of bits being compared to the bit index pattern.

Abstract: A multiplexer includes a transmission-side filter electrically connected to a common terminal and a transmission input terminal, and a transmission-side filter electrically connected to the common terminal and a transmission input terminal. The transmission-side filter includes a plurality of series arm resonators and a plurality of parallel arm resonators. Capacitance elements are respectively electrically connected in parallel to the series arm resonator and the parallel arm resonator, which are connected most proximately to the common terminal. IDT electrodes of a series arm resonator and a parallel arm resonator connected most proximately to the common terminal do not include a thinning electrode, and others of the series arm resonators and the parallel arm resonators include thinning electrodes.

Abstract: A power-on reset circuit 10 has: an enhancement-type PMOS transistor P1 whose source is connected to VDD and whose drain is connected to node VJG; a depletion-type NMOS transistor D1 whose drain is connected to the node VJG; a first resistor portion having resistors R1, R2 that are connected in series, and whose one end is connected to a source of the depletion-type NMOS transistor D1, and whose another end is connected to GND, and at which a region between the resistors R1, R2 is connected to a gate of the enhancement-type PMOS transistor P1; and an inverter whose input is connected to the node VJG, and that outputs a reset signal.

Abstract: A low-power phase interpolator circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts; a phase rotator circuit that outputs phase-adjusted clock signals, each phase-adjusted clock signal having a phase that lies within a range bounded by phases of two of the intermediate clock signals; a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference; and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.

Abstract: A scan driver circuit for an active matrix array includes a plurality of stages and a plurality of decoders that are sequentially driven at different driving timings in a same stage based on a combination of the plural decoder signals or that are driven at the same timing in different stages where a last decoder of the plural decoders sequentially outputs a scan line signal according to a driving state of the plural decoders in each of plural stages, each of the plural decoders includes an input part, an output part and a reset part, and the input part includes a first decoding transistor, a fourth decoding transistor connected to a clock signal and second, third, fifth and sixth decoding transistors connected in series to each of the first decoding transistor and the fourth decoding transistor and connected to the plural decoder signals.

Abstract: Approaches describe a mobile computing device, e.g., an ergonomically configured connected counting device, to capture counts of people, products, or any countable object, store the counts and associated information in a central repository for access by other connected counting devices. The counts and associated qualifying information can then be displayed through mobile devices and web applications, and can display count data with sales, demographic and other qualifying data sources to provide information for qualitative and quantitative reporting, as well as enable count based automated promotions through traditional channels and social networks.

Abstract: An input receiver circuit for a signal line may receive inputs from other signal lines to mitigate crosstalk noise present on the signal line. In some examples, the input receiver circuit may include a transistor with a programmable width. In some examples, the input receiver circuit may include a bias current generator with a programmable current. The width and/or current may be programmed based on an amount of crosstalk noise introduced by the other signal line. In some examples, the input receiver circuit may include a resistance and/or a capacitance. In some examples the resistor and/or capacitor may be programmable. The resistance and/or capacitance may be programmed based on a duration of the crosstalk noise on the signal line.

Abstract: An integrated circuit (IC) includes a level shifter coupled to receive a first supply voltage and a second supply voltage and configured to generate a first output signal and a second output signal in response to an input command signal and an edge detector configured to detect an edge on the second supply voltage and to sink a current from the level shifter in response to detection of the edge in order to prevent a change in logic state of the first output signal or the second output signal. The edge detector can include a positive edge detector configured to generate a positive edge signal in response to detection of a positive going edge of greater than a first predetermined slew rate and a negative edge detector configured to generate a negative edge signal in response to detection of a negative going edge of greater than a second predetermined slew rate.

Abstract: A circuit for sensing local operating properties of an integrated circuit is disclosed. The circuit may include one or more sensor circuits configured to sense the local operating properties of the integrated circuit. The sensor circuits may receive a supply voltage with a magnitude in a limited range from a digital power supply that is different from the digital power supply that provides power to functional circuits in the integrated circuit. Level shifters may be coupled to the sensor circuits to shift output signals from the sensor circuits to levels that correspond to the digital power supply that provides power to functional circuits in the integrated circuit. Counters and a shift register may be coupled to the level shifters to receive the shifted output signals, the values of which may be used to determine the local operating properties of the integrated circuit as sensed by the sensor circuits.