Patents Examined by Tucker Wright
  • Patent number: 9224770
    Abstract: A system and method for reducing cross-talk between photosensitive diodes is provided. In an embodiment a first color filter is formed over a first photosensitive diode and a second color filter is formed over a second photosensitive diode, and a gap is formed between the first color filter and the second color filter. The gap will serve to reflect light that otherwise would have crossed from the first color filter to the second color filter, thereby reducing cross-talk between the first photosensitive diode and the second photosensitive diode. A reflective grid may also be formed between the first photosensitive diode and the second photosensitive diode in order to assist in the reflection and further reduce the amount of cross-talk.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: December 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Shuang-Ji Tsai
  • Patent number: 9224773
    Abstract: A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed at a surface of the semiconductor substrate, wherein the photo-sensitive device is configured to receive a light signal from the backside of the semiconductor substrate, and convert the light signal to an electrical signal. An amorphous-like adhesion layer is disposed on the backside of the semiconductor substrate. The amorphous-like adhesion layer includes a compound of nitrogen and a metal. A metal shielding layer is disposed on the backside of the semiconductor substrate and contacting the amorphous-like adhesion layer.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: December 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chieh Chang, Jian-Shin Tsai, Chih-Chang Huang, Ing-Ju Lee, Ching-Yao Sun, Jyun-Ru Wu, Ching-Che Huang, Szu-An Wu, Ying-Lang Wang
  • Patent number: 9219125
    Abstract: A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: December 22, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Nien Chen, Jin-Aun Ng, Ming Zhu, Bao-Ru Young, Harry-Hak-Lay Chuang
  • Patent number: 9214480
    Abstract: A display device and a method of manufacturing the same are disclosed, in which a sensing electrode for sensing a touch of a user is built in a display panel, whereby a separate touch screen is not required on an upper surface of the display panel unlike the related art and thus thickness and manufacturing cost are reduced.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: December 15, 2015
    Assignee: LG Display Co., Ltd.
    Inventors: JongHyun Park, HyunSeok Hong
  • Patent number: 9214481
    Abstract: An embodiment of the disclosed technology provides a driving device for a thin film transistor liquid crystal display (TFT-LCD) and a method for manufacturing the same. The driving device comprises at least one first TFT and at least one second TFT formed a base substrate, wherein load of the first TFT is larger than load of the second TFT, the first TFT is of a top-gate configuration, and the second TFT is of a bottom-gate configuration.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: December 15, 2015
    Assignee: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Kun Cao, Ming Hu
  • Patent number: 9196789
    Abstract: A reflective contact layer system and a method for forming a reflective contact layer system for an optoelectronic component are disclosed. In an embodiment the component includes a first p-doped nitride compound semiconductor layer, a transparent conductive oxide layer, a minor layer and a second p-doped nitride compound semiconductor layer arranged between the first p-doped nitride compound semiconductor layer and the transparent conductive oxide layer, wherein the second p-doped nitride compound semiconductor layer has N-face domains at an interface facing the transparent conductive oxide layer, and wherein the N-face domains at the interface have an area proportion of at least 95%.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: November 24, 2015
    Assignees: OSRAM Opto Semiconductors GmbH, Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
    Inventors: Matthias Peter, Simeon Katz, Jürgen Off, Korbinian Perzlmaier, Kai Gehrke, Rolf Aidam, Jürgen Däubler, Thorsten Passow
  • Patent number: 9190270
    Abstract: Provided are a low-defect semiconductor device and a method of manufacturing the same. The method includes forming a buffer layer on a silicon substrate, forming an interface control layer on the buffer layer under a first growth condition, and forming a nitride stack on the interface control layer under a second growth condition different from the first growth condition.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: November 17, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-jo Tak, Jae-kyun Kim, Joo-sung Kim, Jun-youn Kim, Young-soo Park, Eun-ha Lee
  • Patent number: 9190422
    Abstract: A display device and a method of manufacturing the same are disclosed, in which a sensing electrode for sensing a touch of a user is built in a display panel, whereby a separate touch screen is not required on an upper surface of the display panel and thus thickness and manufacturing cost are reduced.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: November 17, 2015
    Assignee: LG Display Co., Ltd.
    Inventor: HyunSeok Hong
  • Patent number: 9184111
    Abstract: A wafer-level chip scale package is disclosed, including a chip including a substrate and a GaN transistor disposed on the substrate. The GaN transistor includes a first electrode, a dielectric layer disposed on the chip, and a redistribution trace disposed on the first dielectric layer and electrically connected with the first electrode, wherein the redistribution trace has a linear side and a curved side on opposite sides along its longitudinal direction.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: November 10, 2015
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chia-Yen Lee, Chi-Cheng Lin, Hsin-Chang Tsai
  • Patent number: 9177941
    Abstract: A semiconductor chip 109 is mounted on a substrate 100, first wire group 120 and a second wire group 118 having a wire length shorter than the first wire group are provided so as to connect the substrate 100 and the semiconductor chip 109 to each other, and a sealing resin 307 is injected from the first wire group 120 toward the second wire group 118 so as to form a sealer 401 covering the semiconductor chip 109, the first wire group 120, and the second wire group 118.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: November 3, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Naohiro Handa
  • Patent number: 9165863
    Abstract: Systems and methods for lead frame locking design features are provided. In one embodiment, a method comprises: fabricating a lead frame for a chip package, the lead frame having a paddle comprising a step-out bottom locking feature profile across at least a first segment of an edge of the paddle that provides an interface with a mold compound; etching the paddle to have at least a second segment of the edge having either an extended-step-out bottom locking feature profile or an overhanging top locking feature profile; and alternating first and second segments along the edge of the paddle.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: October 20, 2015
    Assignee: Intersil Americas LLC
    Inventor: Randolph Cruz
  • Patent number: 9166060
    Abstract: To provide a semiconductor device having a structure capable of suppressing deterioration of its electrical characteristics which becomes apparent with miniaturization. The semiconductor device includes a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a source electrode and a drain electrode in contact with the second oxide semiconductor film; a third oxide semiconductor film over the second oxide semiconductor film, the source electrode, and the drain electrode; a gate insulating film over the third oxide semiconductor film; and a gate electrode over the gate insulating film. A first interface between the gate electrode and the gate insulating film has a region closer to the insulating surface than a second interface between the first oxide semiconductor film and the second oxide semiconductor film.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: October 20, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masayuki Sakakura, Hideomi Suzawa, Kazuya Hanaoka
  • Patent number: 9153648
    Abstract: A method for manufacturing a semiconductor stacked body, and a semiconductor element including the semiconductor stacked body includes a semiconductor stacked body, including a Ga2O3 substrate having, as a principal plane, a plane on which oxygen atoms are arranged in a hexagonal lattice, an AlN buffer layer formed on the Ga2O3 substrate, and a nitride semiconductor layer formed on the AlN buffer layer.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: October 6, 2015
    Assignees: TAMURA CORPORATION, KOHA CO, LTD.
    Inventors: Shinkuro Sato, Akito Kuramata, Yoshikatsu Morishima, Kazuyuki Iizuka
  • Patent number: 9142558
    Abstract: A semiconductor device includes a plurality of lower electrodes having a vertical length greater than a horizontal width on a substrate, a supporter disposed between the lower electrodes, an upper electrode disposed on the lower electrodes, and a capacitor dielectric layer disposed between the lower electrodes and the upper electrode. The supporter includes a first element, a second element, and oxygen, an oxide of the second element has a higher band gap energy than an oxide of the first element, and the content of the second element in the supporter is from about 10 at % to 90 at %.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: September 22, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Jeong Yang, Soon-Wook Jung, Bong-Jin Kuh, Wan-Don Kim, Byung-Hong Chung, Yong-Suk Tak
  • Patent number: 9136293
    Abstract: Methods and apparatus for integrating a CMOS image sensor and an image signal processor (ISP) together using an interposer to form a system in package device module are disclosed. The device module may comprise an interposer with a substrate. An interposer contact is formed within the substrate. A sensor device may be bonded to a surface of the interposer, wherein a sensor contact is bonded to a first end of the interposer contact. An ISP may be connected to the interposer, by bonding an ISP contact in the ISP to a second end of the interposer contact. An underfill layer may fill a gap between the interposer and the ISP. A printed circuit board (PCB) may further be connected to the interposer by way of a solder ball connected to another interposer contact. A thermal interface material may be in contact with the ISP and the PCB.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: September 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chung Yee, Chun Hui Yu
  • Patent number: 9130077
    Abstract: An image sensor device and a method for manufacturing the image sensor device are provided. An image sensor device includes a substrate, sensor elements disposed at a front surface of the substrate, and a dielectric grid disposed over a back surface of the substrate. The dielectric grid includes a first dielectric layer as a bottom portion, a metal pillar, as a core portion of a upper portion, disposed over the first dielectric layer and a second dielectric layer wrapping around the metal pillar. The image sensor device also includes a stack of layers disposed over the back surface of the substrate. Refractive index of each layers increases from top layer to bottom layer. The image sensor device also includes a color filter and a microlens disposed over the back surface of the substrate.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: September 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ssu-Chiang Weng, Kuo-Cheng Lee, Chi-Cherng Jeng
  • Patent number: 9129687
    Abstract: A one time programmable memory cell having twin wells to improve dielectric breakdown while minimizing current leakage. The memory cell is manufactured using a standard CMOS process used for core and I/O (input/output) circuitry. A two transistor memory cell having an access transistor and an anti-fuse device, or a single transistor memory cell 100 having a dual thickness gate oxide 114 & 116, are formed in twin wells 102 & 104. The twin wells are opposite in type to each other, where one can be an N-type well 102 while the other can be a P-type well 104. The anti-fuse device is formed with a thin gate oxide and in a well similar to that used for the core circuitry. The access transistor is formed with a thick gate oxide and in a well similar to that used for I/O circuitry.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: September 8, 2015
    Assignee: Sidense Corp.
    Inventor: Wlodek Kurjanowicz
  • Patent number: 9123887
    Abstract: A magnetic electronic device comprises a substrate, a buffer layer, a first CoFeB layer, a first metal oxidation layer and a capping layer. The buffer layer is disposed above the substrate. The first CoFeB layer is disposed above the buffer layer. The first metal oxidation layer is disposed above the first CoFeB layer. The capping layer is disposed above the first metal oxidation layer and covers the first metal oxidation layer. A manufacturing method of the magnetic electronic device is also disclosed.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: September 1, 2015
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Chih-Huang Lai, Ding-Shuo Wang
  • Patent number: 9112124
    Abstract: With a light emitting device of a package formed by two types of molded resins, entry of water from between the molded resins may cause the light emitting device to be incapable of turning on. A light emitting device of the present invention includes: a package that has an opening at an upper surface thereof; a first molded resin that forms a part of the upper surface of the package; a second molded resin that forms an inner wall surface of the opening of the package; a lead frame that is buried in the package so as to be partially exposed at a bottom surface of the opening of the package, the lead frame having an end portion externally projected outside from a side surface of the package; and a light emitting element that is connected to an upper surface of the lead frame being exposed at the bottom surface of the opening. The second molded resin is higher than the first molded resin in light reflectance to light emitted from the light emitting element.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: August 18, 2015
    Assignee: NICHIA CORPORATION
    Inventors: Tetsuya Yagi, Yuki Miyaura
  • Patent number: 9111823
    Abstract: An image sensor having a sensor array area, a circuit area around the sensor array area, and a pad area adjacent to the circuit area includes a substrate, a multi-layer wiring structure including a plurality of wiring layers on a first surface of the substrate in the circuit area, at least one well in the substrate in the circuit area, and metal wiring that extends on a second surface of the substrate opposite to the first surface, from the pad area to the circuit area, and extends from the second surface into contacts with the at least one well.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: August 18, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Ho Kim, Duck-Hyung Lee, Young-Hoon Park