Abstract: A display substrate including a base substrate having a switching device, a first insulating layer over the base substrate having a contact hole partially exposing an electrode of the switching device, a first electrode over the first insulating layer, a second insulating layer over the first electrode, and a second electrode over the second insulating layer, wherein at least one of the first electrode and the second electrode is coupled to the electrode of the switching device through the contact hole, wherein at least one of the first electrode and the second electrode is formed in regions other than a peripheral region of the contact hole to prevent delamination and shorting of the pixel and common electrodes.

Abstract: The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer.

Abstract: A multi-chip electronic package and methods of manufacture are provided. The multi-chip package includes a plurality of chips mounted on a chip carrier. The multi-chip package further includes a lid mounted on the chip carrier using a bonding material or compression seal, and at least one single piston extending from the lid. Each piston covers an entirety of multiple chips of the plurality of chips.

Abstract: A channel region of a finFET has fins having apexes in a first direction parallel to a surface of a substrate, each fin extending downwardly from the apex, with a gate overlying the apexes and between adjacent fins. A semiconductor stressor region extends in at least the first direction away from the fins to apply a stress to the channel region. Source and drain regions of the finFET can be separated from one another by the channel region, with the source and/or drain at least partly in the semiconductor stressor region. The stressor region includes a first semiconductor region and a second semiconductor region overlying and extending from the first semiconductor region. The second semiconductor region can be more doped than the first semiconductor region, and the first and second semiconductor regions can have opposite conductivity types where a portion of the second semiconductor region meets the first semiconductor region.

Abstract: Display substrates are disclosed. In one aspect, display substrates include a first signal line, a second signal line, a first detour signal line and a second detour signal line. The first signal line includes a first region and a pair of second regions disposed on opposite sides of the first region. The pair of second regions are spaced apart from the first region. The second signal line crosses the first signal line. The second signal line includes a third region and a pair of fourth regions disposed on opposite sides of the third region. The pair of fourth regions are spaced apart from the third region. The first detour signal line electrically connects the pair of second regions to each other. The second detour signal line electrically connects the pair of fourth regions to each other. Related methods are also disclosed.

Abstract: The invention provides a semiconductor device, including: a substrate having a first conductivity type, including: a body region having the first conductivity type; a source region formed in the body region; a drift region having a second conductivity type adjacent to the body region; and a drain region formed in the drift region; a multiple reduced surface field (RESURF) structure embedded in the drift region of the substrate; and a gate dielectric layer formed over the substrate; wherein the first conductivity type is opposite to the second conductivity type.

Abstract: A memory array includes a plurality of digitline (DL) trenches extending along a first direction; a buried digitline between the DL trenches; a trench fill material layer sealing an air gap in each of the DL trenches; a plurality of wordline (WL) trenches extending along a second direction; an active chop (AC) trench disposed at one end of the buried digitline; a shield layer in the air gap; and a sidewall conductor around the sidewall of the AC trench.

Abstract: A field effect transistor (FET) having fingers with rippled edges is disclosed. The FET includes a semiconductor substrate having a front side with a finger axis. A drain finger is disposed on the front side of the semiconductor substrate such that a greatest dimension of the drain finger lies parallel to the finger axis. A gate finger is disposed on the front side of the semiconductor substrate. The gate finger is spaced from the drain finger such that a greatest dimension of the gate finger lies parallel to the finger axis. A source finger is disposed on the front side of the semiconductor substrate. The source finger is spaced from the gate finger such that a greatest dimension of the source finger lies parallel to the finger axis. The drain finger, the gate finger, and the source finger each have rippled edges with an axis parallel with the finger axis.

Abstract: According to one embodiment, an image sensor includes an image-sensing element region formed by arranging a plurality of image-sensing elements on a semiconductor substrate, and a logic circuit region formed in a region different from the image-sensing element region on the substrate and including a plurality of gate patterns. Further, dummy gate patterns are formed with a constant pitch on the image-sensing element region.

Abstract: A field effect transistor (FET) includes a III-Nitride channel layer, a III-Nitride barrier layer on the channel layer, wherein the barrier layer has an energy bandgap greater than the channel layer, a source electrode electrically coupled to one of the III-Nitride layers, a drain electrode electrically coupled to one of the III-Nitride layers, a gate insulator layer stack for electrically insulating a gate electrode from the barrier layer and the channel layer, the gate insulator layer stack including an insulator layer, such as SiN, and an AlN layer, the gate electrode in a region between the source electrode and the drain electrode and in contact with the insulator layer, and wherein the AlN layer is in contact with one of the III-Nitride layers.

Abstract: A semiconductor device includes a gate pattern over source and drain regions. The gate pattern includes a first gate adjacent the source region and a second gate adjacent the drain region. A concentration of dopants in the first gate is higher than a concentration of dopants in the second gate. As a result, channels are produced between the source and drain regions based on different threshold voltages.

Abstract: Scalable Gate Logic Non-Volatile Memory (SGLNVM) devices fabricated with the conventional CMOS process is disclosed. Floating gates of SGLNVM with the minimal length and width of the logic gate devices form floating gate Metal-Oxide-Semiconductor Field Effect Transistor. The floating gates with the minimal gate length extend over silicon active areas to capacitively couple control gates embedded in silicon substrate (well) through an insulation dielectric. The embedded control gate is formed by a shallow semiconductor type opposite to the type of the silicon substrate or well. Plurality of SGLNVM devices are configured into a NOR-type flash array where a pair of SGLNVM devices share a common source electrode connected to a common ground line with two drain electrodes connected to two separate bitlines. The pairs of the NOR-type SGLNVM cells are physically separated and electrically isolated by dummy floating gates to minimize cell sizes.

Abstract: An object is to reduce parasitic capacitance of a signal line included in a liquid crystal display device. A transistor including an oxide semiconductor layer is used as a transistor provided in each pixel. Note that the oxide semiconductor layer is an oxide semiconductor layer which is highly purified by thoroughly removing impurities (hydrogen, water, or the like) which become electron suppliers (donors). Thus, the amount of leakage current (off-state current) can be reduced when the transistor is off. Therefore, a voltage applied to a liquid crystal element can be held without providing a capacitor in each pixel. In addition, a capacitor wiring extending to a pixel portion of the liquid crystal display device can be eliminated. Therefore, parasitic capacitance in a region where the signal line and the capacitor wiring intersect with each other can be eliminated.

Abstract: A semiconductor device includes, a semiconductor substrate, a plurality of memory cells being provided on the semiconductor substrate in a memory cell region. Each of the plurality of memory cells having a first gate electrode disposed on the semiconductor substrate with a first gate insulating film, and the first gate electrode having a first charge storage layer, a first inter-electrode insulating film and a first control gate electrode film, and a cavity is interposed between an upper surface of the charge storage layer and the inter-electrode insulating film.

Abstract: A semiconductor structure includes a SOI/BOX semiconductor substrate, a device, a deep trench, a silicon layer, and a dielectric layer. The deep trench is adjacent to the device and extends through a shallow trench isolation layer within the SOI layer and the BOX layer and into the base semiconductor substrate. The silicon layer is disposed within a lower portion of the deep trench. The silicon layer has a top surface height substantially the same as or lower than a top surface height of the base semiconductor substrate. The dielectric layer is disposed within the deep trench and on the silicon layer. The deep trench can be formed before or after formation of an interlayer dielectric.

Abstract: An epitaxial growth method includes the steps of: providing a substrate; forming a sacrifice layer on the substrate; patterning the sacrifice layer to form a plurality of bumps spaced apart from each other on the substrate; epitaxially forming a first epitaxial layer on the substrate to cover a portion of each of the bumps; removing the bumps to form a plurality of cavities; and epitaxially forming a second epitaxial layer on the first epitaxial layer such that the cavities are enclosed by the first epitaxial layer and the second epitaxial layer. An epitaxial structure grown by the method is disclosed as well.

Abstract: The organic thin-film transistor according to the present invention includes: a gate electrode line on a substrate in a first region: a first signal line layer in a second region; a gate insulating film covering the gate electrode line and the first signal line layer; bank layers on the gate insulating film; a second signal line layer on the bank layer over the first signal line; a drain electrode and a source electrode line which are located on the bank layers and in at least one opening between the bank layers in the first region; a semiconductor layer located at least in the opening and banked up by the bank layers, the drain electrode, and the source electrode line; and a protection film covering the semiconductor layer.

Abstract: This semiconductor device (100) includes a substrate (1), a gate electrode (11), a gate insulating film (12), an oxide semiconductor layer (13), a source electrode (14), a drain electrode (15), and a protective film (16). The upper and side surfaces of the oxide semiconductor layer are covered with the source and drain electrodes and the protective film. When viewed along a normal to the substrate, the narrowest gap between the respective outer peripheries of a first contact region (13s) and the source electrode and the narrowest gap between the respective outer peripheries of a second contact region (13d) and the drain electrode both have a length of 1.5 ?m to 4.5 ?m.

Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes an isolation structure formed in a substrate to define an active region of the substrate. The active region has a field plate region therein. A step gate dielectric structure is formed on the substrate in the field plate region. The step gate dielectric structure includes a first layer of a first dielectric material and a second layer of the dielectric material, laminated vertically to each other. The first and second layers of the first dielectric material are separated from each other by a second dielectric material layer. An etch rate of the second dielectric material layer to an etchant is different from that of the second layer of the first dielectric material. A method for forming a semiconductor device is also disclosed.

Abstract: Device structures and design structures that include a silicon controlled rectifier, as well as fabrication methods for such device structures. A well is formed in the device layer of a silicon-on-insulator substrate. A silicon controlled rectifier is formed that includes an anode in the well. A deep trench capacitor is formed that includes a plate coupled with the well. The plate of the deep trench capacitor extends from the device layer through a buried insulator layer of the silicon-on-insulator substrate and into a handle wafer of the silicon-on-insulator substrate.