Abstract: An inventive semiconductor device includes a semiconductor layer, a source region provided in a surface layer portion of the semiconductor layer, a drain region provided in the surface of the semiconductor layer in spaced relation from the source region, a gate insulation film provided in opposed relation to a portion of the surface of the semiconductor layer present between the source region and the drain region, a gate electrode provided on the gate insulation film, and a drain-gate isolation portion provided between the drain region and the gate insulation film for isolating the drain region and the gate insulation film from each other in non-contact relation.

Abstract: The present invention provides Schottky-like and ohmic contacts comprising metal oxides on zinc oxide substrates and a method of forming such contacts. The metal oxide Schottky-like and ohmic contacts may be formed on zinc oxide substrates using various deposition and lift-off photolithographic techniques. The barrier heights of the metal oxide Schottky-like contacts are significantly higher than those for plain metals and their ideality factors are very close to the image force controlled limit. The contacts may have application in diodes, power electronics, FET transistors and related structures, and in various optoelectronic devices, such as UV photodetectors.

Abstract: An object is to reduce parasitic capacitance of a signal line included in a liquid crystal display device. A transistor including an oxide semiconductor layer is used as a transistor provided in each pixel. Note that the oxide semiconductor layer is an oxide semiconductor layer which is highly purified by thoroughly removing impurities (hydrogen, water, or the like) which become electron suppliers (donors). Thus, the amount of leakage current (off-state current) can be reduced when the transistor is off. Therefore, a voltage applied to a liquid crystal element can be held without providing a capacitor in each pixel. In addition, a capacitor wiring extending to a pixel portion of the liquid crystal display device can be eliminated. Therefore, parasitic capacitance in a region where the signal line and the capacitor wiring intersect with each other can be eliminated.

Abstract: According to one embodiment, a magnetoresistive effect element includes a first magnetic layer including perpendicular anisotropy to a film surface and an invariable magnetization direction, the first magnetic layer having a magnetic film including an element selected from a first group including Tb, Gd, and Dy and an element selected from a second group including Co and Fe, a second magnetic layer including perpendicular magnetic anisotropy to the film surface and a variable magnetization direction, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer. The magnetic film includes amorphous phases and crystals whose particle sizes are 0.5 nm or more.

Abstract: A semiconductor device and a manufacturing method thereof are provided. In one embodiment of the manufacturing method of the semiconductor device, a through electrode is formed on a semiconductor die, and a dielectric layer such as a photopolymer is coated on the through electrode to cover the through electrode. Under exposure is performed on the dielectric layer, thereby partially removing the dielectric layer by development. As a result, a top end of the through electrode is exposed to the outside or protrudes through the dielectric layer. The dielectric layer remaining on the top end of the through electrode may be removed by performing a plasma descum process, if needed.

Abstract: A high density deep trench MIM capacitor structure is provided wherein conductive-compressive-conformally applied layers of a semiconductor material, such as a Poly-SixGe1-x, are interleaved within MIM capacitor layers to counterbalance the tensile stresses created by such MIM capacitor layers. The interleaving of conductive-compressive-conformally applied material layers are adapted to counterbalance convex (upward) bowing of silicon wafers during the manufacturing process of high density deep trench MIM capacitor silicon devices to thereby help maximize production yields of such devices per wafer.

Abstract: An architecture, circuit and method for providing a very dense, producible, non volatile FLASH memory with SONOS cells. SONOS memory cells are formed using a uniformly doped channel region. A FinFET embodiment cell is disclosed. Because the novel SONOS cells do not rely on diffused regions, the cells may be formed into a three dimensional array of cells without diffusion problems. FLASH memory arrays are formed by forming layers of NAND Flash cells in the local interconnect layers of an integrated circuit, with the metal layers forming the global bit line conductors. The three dimensional non-volatile arrays formed of the SONOS cells rely on conventional semiconductor processing. P-channel and n-channel devices may be used to form the SONOS non-volatile cells.

Abstract: Provided is a three-dimensional semiconductor device and method for fabricating the same. The device includes a first electrode structure and a second electrode structure stacked sequentially on a substrate. The first and second electrode structures include stacked first electrodes and stacked second electrodes, respectively. Each of the first and second electrodes includes a horizontal portion parallel with the substrate and an extension portion extending from the horizontal portion along a direction penetrating an upper surface of the substrate. Here, the substrate may be closer to top surfaces of the extension portions of the first electrodes than to the horizontal portion of at least one of the second electrodes.

Abstract: The present invention relates to a thin film transistor and a method of manufacturing the same. More particularly, the present invention relates to a thin film transistor that includes a zinc oxide (ZnO series) electrode having one or more of Si, Mo, and W as a source electrode and a drain electrode, and a method of manufacturing the same.

Abstract: An isolation area that provides additional active area between semiconductor devices on an integrated circuit is described. In one embodiment, the invention includes a complementary metal oxide semiconductor transistor of an image sensor having a source, a drain, and a gate between the source and the drain, the transistor having a channel to couple the source and the drain under the influence of the gate, and an isolation barrier surrounding a periphery of the source and the drain to isolate the source and the drain from other devices, wherein the isolation barrier is distanced from the central portion of the channel.

Abstract: This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.

Abstract: Disclosed is a semiconductor device which includes a substrate 11, a thin film transistor 20 having a first semiconductor layer 16A that is supported by the substrate 11, a thin film diode 30 having a second semiconductor layer 16B that is supported by the substrate 11, and a metal layer 12 that is formed between the substrate 11 and the second semiconductor layer 16B. The first semiconductor layer 16A is a laterally grown crystalline semiconductor film, and the second semiconductor layer 16B is a crystalline semiconductor film that contains fine crystal grains. The average surface roughness of the second semiconductor layer 16B is higher than the average surface roughness of the first semiconductor layer 16A. Consequently, the optical sensitivity of the TFD is improved and the reliability of the TFT is improved, as compared with those in the conventional semiconductor devices.

Abstract: A photodiode is provided according to various embodiments. In some embodiments, the photodiode includes a substrate and an active region. The active region is configured to receive light through the substrate. In such a configuration, the substrate not only participates in the photodiode operation acts as a light filter depending on the substrate material. In some embodiments, the active region may include solder balls that may be used to couple the photodiode to a printed circuit board. In some embodiments, the active region is coupled face-to-face with the printed circuit board.

Abstract: A method of manufacturing a semiconductor device is disclosed and starts with a semiconductor substrate having a heavily doped N region at the bottom main surface and having a lightly doped N region at the top main surface. There are a plurality of trenches in the substrate, with each trench having a first extending portion extending from the top main surface towards the heavily doped region. Each trench has two sidewall surfaces in parallel alignment with each other. A blocking layer is formed on the sidewalls and the bottom of each trench. Then a P type dopant is obliquely implanted into the sidewall surfaces to form P type doped regions. The blocking layer is then removed. The bottom of the trenches is then etched to remove any implanted P type dopants. The implants are diffused and the trenches are filled.

Abstract: A high voltage device includes drift regions formed in a substrate, an isolation layer formed in the substrate to isolate neighboring drift regions, wherein the isolation layer has a depth greater than that of the drift region, a gate electrode formed over the substrate, and source and drain regions formed in the drift regions on both sides of the gate electrode.

Abstract: A vertical NAND flash memory device includes a substrate having a face and a string of serially connected flash memory cells on the substrate. A first flash memory cell is adjacent the face, and a last flash memory cell is remote from the face. The flash memory cells include repeating layer patterns that are stacked on the face, and a pillar that extends through the series of repeating layer patterns. The pillar includes at least one oblique wall. At least two of the series of repeating layer patterns in the string are of different thicknesses. Other vertical microelectronic devices and related fabrication methods are also described.

Abstract: A method and structures are provided for implementing metal via gate node high performance stacked vertical transistors in a back end of line (BEOL) on a semiconductor System on Chip (SoC). The high performance stacked vertical transistors include a pair of stacked vertical field effect transistors (FETs) formed by polycrystalline depositions in a stack between planes of a respective global signal routing wire. A channel length of each of the stacked vertical FETs is delineated by the polycrystalline depositions with sequential source deposition, channel deposition and drain deposition; and a wire via defines the gate node.

Abstract: A three-dimensional semiconductor device includes stacked structures arranged two-dimensionally on a substrate, a first interconnection layer including first interconnections and disposed on the stacked structures, and a second interconnection layer including second interconnections and disposed on the first interconnection layer. Each of the stacked structures has a lower region including a plurality of stacked lower word lines, and an upper region including a plurality of stacked upper word lines disposed on the stack of lower word lines. Each of the first interconnections is connected to one of the lower word lines and each of the second interconnections is connected to one of the upper word lines.

Abstract: A mesa type semiconductor device and its manufacturing method are offered to increase a withstand voltage as well as reducing a leakage current. An N?-type semiconductor layer is formed on a surface of a semiconductor substrate, and a P-type semiconductor layer is formed on the N?-type semiconductor layer. After that, a mesa groove is formed by etching the P-type semiconductor layer, a PN junction, the N?-type semiconductor layer and a partial thickness of the semiconductor substrate so that a width of the mesa groove grows from a surface of the P-type semiconductor layer toward the semiconductor substrate. Subsequent wet etching removes a damaged layer in an inner wall of the mesa groove caused by the preceding etching and transforms the mesa groove in a region close to a surface of the P-type semiconductor layer so that a width of the mesa groove increases toward the surface of the P-type semiconductor layer. After that, the semiconductor substrate and the layers stacked on it are diced.

Abstract: An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, an oxide-based barrier layer directly on sidewalls of the opening, and conductive materials filling the remaining portion of the opening.