Patents Examined by Tucker Wright
  • Semiconductor device with stacked semiconductor chips
    Patent number: 8610288
    Abstract: A semiconductor chip 109 is mounted on a substrate 100, first wire group 120 and a second wire group 118 having a wire length shorter than the first wire group are provided so as to connect the substrate 100 and the semiconductor chip 109 to each other, and a sealing resin 307 is injected from the first wire group 120 toward the second wire group 118 so as to form a sealer 401 covering the semiconductor chip 109, the first wire group 120, and the second wire group 118.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: December 17, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Naohiro Handa
  • Electroluminescent organic semiconductor element and a method for repair of an electroluminescent organic semiconductor element
    Patent number: 8610116
    Abstract: An electroluminescent organic semiconductor element includes a substrate and a first electrode arranged on the substrate. The semiconductor element additionally contains a second electrode and at least one organic layer, which is arranged between the first electrode and the second electrode. The organic layer is a layer that generates light by recombination of charge carriers. At least one of the first and the second electrode contains a highly conductive organic sublayer.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: December 17, 2013
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Markus Klein, Tilman Schlenker
  • Semiconductor having a high aspect ratio via
    Patent number: 8598687
    Abstract: The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: December 3, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yuan-Chih Hsieh, Richard Chu, Ming-Tung Wu, Martin Liu, Lan-Lin Chao, Chia-Shiung Tsai
  • Semiconductor structure and method for manufacturing the same
    Patent number: 8598666
    Abstract: The present invention relates to a semiconductor structure and a method for manufacturing the same.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: December 3, 2013
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Haizhou Yin, Zhijiong Luo
  • Thin film wafer level package
    Patent number: 8592998
    Abstract: Anchor designs for thin film packages are disclosed that, in a preferred embodiment are a combination of SiGe-filled trenches and Si-oxide-filled spacing. Depending on the release process, additional manufacturing process steps are performed in order to obtain a desired mechanical strength. For aggressive release processes, additional soft sputter etch and a Ti—TiN interlayer in the anchor region may be added. The ratio of the total SiGe—SiGe anchor area to the SiO2—SiGe anchor area determines the mechanical strength of the anchor. If this ratio is larger than 1, the thin film package reaches the MIL-standard requirements.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: November 26, 2013
    Assignees: IMEC, Katholieke Universiteit Leuven, KU LEUVEN R&D
    Inventors: Gert Claes, Ann Witvrouw
  • Coupling well structure for improving HVMOS performance
    Patent number: 8592923
    Abstract: A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: November 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsueh-Liang Chou, Chen-Bau Wu, Weng-Chu Chu, Tsung-Yi Huang, Fu-Jier Fan
  • Integrated circuit including vertical diode
    Patent number: 8586960
    Abstract: An integrated circuit includes a substrate including isolation regions, a first conductive line formed in the substrate between isolation regions, and a vertical diode formed in the substrate. The integrated circuit includes a contact coupled to the vertical diode and a memory element coupled to the contact. The first conductive line provides a portion of the vertical diode.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: November 19, 2013
    Assignees: International Business Machines Corporation, Macronix International Co., Ltd., Qimonda AG
    Inventors: Thomas Happ, Hsiang-Lan Lung, Bipin Rajendran, Min Yang
  • Multichip electronic packages and methods of manufacture
    Patent number: 8587114
    Abstract: A multi-chip electronic package and methods of manufacture are provided. The multi-chip package includes a plurality of chips mounted on a chip carrier. The multi-chip package further includes a lid mounted on the chip carrier using a bonding material or compression seal, and at least one single piston extending from the lid. Each piston covers an entirety of multiple chips of the plurality of chips.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: November 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Suresh D. Kadakia, Kamal K. Sikka, Hilton T. Toy, Jeffrey A. Zitz
  • Silicon-on-insulator (“SOI”) transistor test structure for measuring body-effect
    Patent number: 8586981
    Abstract: According to one exemplary embodiment, a silicon-on-insulator (SOI) transistor test structure includes a gate situated over a semiconductor body and a doped halo under the gate. The SOI transistor test structure further includes at least two semiconductor body contacts situated on opposing sides of the doped halo, where one or more of the at least two semiconductor body contacts forms a direct electrical contact with the doped halo, thereby increasing current flow to the doped halo to facilitate measuring body-effect in the SOI transistor test structure.
    Type: Grant
    Filed: October 5, 2006
    Date of Patent: November 19, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Qiang Chen, Jung-Suk Goo
  • Semiconductor package module and electric circuit assembly with the same
    Patent number: 8581394
    Abstract: Disclosed herein is a semiconductor package module. The semiconductor package module includes a circuit substrate having an external connection pattern; electronic components mounted on the circuit substrate; a molding structure having a structure surrounding the circuit substrate so as to seal the electronic components from the external environment; and an external connection structure of which one portion is connected to the external connection pattern and the other portion is exposed to the outside of the molding structure.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: November 12, 2013
    Assignee: Samsung Electro-Mechanics Co., Ltd
    Inventors: Seung Wook Park, Young Do Kweon, Mi Jin Park
  • Group III-V semiconductor device with strain-relieving interlayers
    Patent number: 8575660
    Abstract: According to one exemplary embodiment, a group III-V semiconductor device includes at least one transition layer situated over a substrate. The group III-V semiconductor device further includes a first strain-relieving interlayer situated over the at least one transition layer and a second strain-relieving interlayer situated over the first strain-relieving interlayer. The group III-V semiconductor device further includes a first group III-V semiconductor body situated over the second strain-relieving interlayer. The first and second strain-relieving interlayers comprise different semiconductor materials so as to reduce a strain in the first group III-V semiconductor body. The second strain-relieving interlayer can be substantially thinner than the first strain-relieving interlayer.
    Type: Grant
    Filed: October 14, 2009
    Date of Patent: November 5, 2013
    Assignee: International Rectifier Corporation
    Inventors: Scott Nelson, Ronald Birkhahn, Brett Hughes
  • Implementing vertical signal repeater transistors utilizing wire vias as gate nodes
    Patent number: 8575613
    Abstract: A method and structures are provided for implementing vertical transistors utilizing wire vias as gate nodes. The vertical transistors are high performance transistors fabricated up in the stack between the planes of the global signal routing wire, for example, used as vertical signal repeater transistors. An existing via or a supplemental vertical via between wire planes provides both an electrical connection and the gate node of the novel vertical transistor.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: November 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams
  • Semiconductor device having isolation groove and device formation portion
    Patent number: 8564037
    Abstract: A semiconductor device may include, but is not limited to, a semiconductor substrate having a device isolation groove defining first to fourth device formation portions. The second device formation portion is separated from the first device formation portion. The third device formation portion extends from the first device formation portion. The third device formation portion is separated from the second device formation portion. The fourth device formation portion extends from the second device formation portion. The fourth device formation portion is separated from the first and third device formation portions. The third and fourth device formation portions are positioned between the first and second device formation portions.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: October 22, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Takeshi Kishida
  • Solid-state imaging device and method for manufacturing the same
    Patent number: 8558338
    Abstract: There are provided semiconductor substrate, ground layer formed on semiconductor substrate and having an upper surface corresponding to pixel region, the upper surface being lower than an upper surface corresponding to peripheral circuit region, a plurality of color filters disposed two-dimensionally on the upper surface corresponding to pixel region in ground layer, and partition wall provided between color filters. In a section which is orthogonal to the upper surface corresponding to pixel region in ground layer, an occupied area of partition wall provided in outer portion disposed in contact with peripheral circuit region is smaller than that of partition wall provided in central portion of pixel region.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: October 15, 2013
    Assignee: Panasonic Corporation
    Inventor: Shoichiro Tsuji
  • Semiconductor device, solid-state imaging device, method for manufacturing semiconductor device, method for manufacturing solid-state imaging device, and electronic apparatus
    Patent number: 8558340
    Abstract: Disclosed herein is a semiconductor device including an element isolation region configured to be formed on a semiconductor substrate, wherein the element isolation region is formed of a multistep trench in which trenches having different diameters are stacked and diameter of an opening part of the lower trench is smaller than diameter of a bottom of the upper trench.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: October 15, 2013
    Assignee: Sony Corporation
    Inventor: Yuki Miyanami
  • Semiconductor device having gate insulating film including high dielectric material
    Patent number: 8558321
    Abstract: A semiconductor device includes: a first MIS transistor of a first conductivity type having a first active region as a region of a semiconductor substrate surrounded by an element isolation region formed in an upper portion of the semiconductor substrate, a first gate insulating film having a first high dielectric film formed on the first active region, and a first gate electrode formed on the first gate insulating film; and a resistance element having a second high dielectric film formed on the element isolation region and a resistance layer made of silicon formed on the second high dielectric film. The first high dielectric film and the second high dielectric film include the same high dielectric material, and the first high dielectric film includes a first adjustment metal, but the second high dielectric film does not include the first adjustment metal.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: October 15, 2013
    Assignee: Panasonic Corporation
    Inventors: Hiroji Shimizu, Yoshihiro Sato, Hideyuki Arai, Takayuki Yamada, Tsutomu Oosuka
  • III-nitride power semiconductor device
    Patent number: 8525224
    Abstract: A III-nitride power semiconductor device that includes a first III-nitride power semiconductor device and a second III-nitride power semiconductor device formed in a common semiconductor die and operatively integrated to form a half-bridge.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: September 3, 2013
    Assignee: International Rectifier Corporation
    Inventor: Daniel M Kinzer
  • Shielding device
    Patent number: 8513782
    Abstract: One aspect of the invention relates to a shielding device for shielding from electromagnetic radiation, including a shielding base element, a shielding cover element and a shielding lateral element for electrically connecting the base element to the cover element in such that a circuit part to be shielded is arranged within the shielding elements. Since at least one partial section of the shielding elements includes a semiconductor material, a shielding device can be realized completely and cost-effectively in an integrated circuit.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: August 20, 2013
    Assignee: Infineon Technologies AG
    Inventors: Winfried Bakalski, Bernd Eisener, Uwe Seidel, Markus Zannoth
  • Low-voltage structure for high-voltage electrostatic discharge protection
    Patent number: 8513774
    Abstract: An electrostatic discharge (ESD) protected device may include a substrate, an N+ doped buried layer, an N-type well region and a P-type well region. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may be disposed proximate to a portion of the N+ doped buried layer to form a collector region. The P-type well region may be disposed proximate to remaining portions of the N+ doped buried layer and having at least a P+ doped plate corresponding to a base region and distributed segments of N+ doped plates corresponding to an emitter region.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: August 20, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Hsin-Liang Chen, Chan Wing Chor
  • CMOS devices incorporating hybrid orientation technology (HOT) with embedded connectors
    Patent number: 8513779
    Abstract: The present invention relates to complementary devices, such as n-FETs and p-FETs, which have hybrid channel orientations and are connected by conductive connectors that are embedded in a semiconductor substrate. Specifically, the semiconductor substrate has at least first and second device regions of different surface crystal orientations (i.e., hybrid orientations). An n-FET is formed at one of the first and second device regions, and a p-FET is formed at the other of the first and second device regions. The n-FET and the p-FET are electrically connected by a conductive connector that is located between the first and second device regions and embedded in the semiconductor substrate. Preferably, a dielectric spacer is first provided between the first and second device regions and recessed to form a gap therebetween. The conductive connector is then formed in the gap above the recessed dielectric spacer.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: August 20, 2013
    Assignee: International Business Machines Corporation
    Inventors: Byeong Y. Kim, Xiaomeng Chen, Yoichi Otani