Patents Examined by Tyrone V. Walker
  • Patent number: 5995728
    Abstract: A computer implemented method to generate and display objectives for evaluating decision alternatives is disclosed. The method begins by computer system working interactively with the decision maker in identifying and displaying alternative solutions to a decision. Pros and cons of the alternatives are then identified by the decision maker with the assistance of the computer and displayed by the computer. Significantly, the pros and cons are used by the decision maker to identify and to be converted into objectives. The objectives, which are the key to a rational evaluation of the alternatives are then structured and displayed by the computer hierarchically in preparation for evaluation and choice by the decision maker. The decision maker then decides on a particular course of action based on the hierarchically displayed objectives.
    Type: Grant
    Filed: May 21, 1996
    Date of Patent: November 30, 1999
    Inventor: Ernest H. Forman
  • Patent number: 5903470
    Abstract: In the case where a multiplier factor is a constant, if the number of the bits having the value of 1 in the multiplier factor is 3 or more and if it is larger than the number of the bits having the value of 0, a circuit for performing multiplication by using the logic NOT number of the multiplier factor, which is obtained by inverting all the bits in the multiplier factor by the logic NOT operation is generated. If the number of the bits having the value of 1 in the multiplier factor is 3 or more and if it is smaller than the number of the bits having the value of 0, the multiplier factor is divided so that an adder for adding partial products forms a well-balanced binary tree. Conversely, if the number of the bits having the value of 1 in the multiplier factor is 2 or less, an add shift multiplier for calculating partial products only with respect to the bits having the value of 1 is generated.
    Type: Grant
    Filed: January 23, 1996
    Date of Patent: May 11, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akira Miyoshi, Tamotsu Nishiyama
  • Patent number: 5870590
    Abstract: A system and apparatus for generating an extended finite state machine (EFSM) from a specification expressed as a set of data relationships. The specification is written in a specification language designed for the purpose, and is parsed in a conventional fashion. The parsed specification is used as input to the method of the invention, which comprises routines for transforming it into an EFSM including states and transitions. The EFSM thus generated is used as input to a traversal procedure, for ultimately generating validation tests to verify the operation of an implementation of the specification, with one such test being generated for each path traversed through the EFSM. The traversal of the EFSM may be carried out in a conventional fashion or by using applicant's EFSM traversal method. The EFSM's transitions represent functions and test information, and the states represent the status of the EFSM at particular points, given the traversal of a particular path through the EFSM, i.e.
    Type: Grant
    Filed: September 15, 1997
    Date of Patent: February 9, 1999
    Inventors: Ronald Allen Kita, Mark Edward Trumpler, Lois Scirocco Elkind
  • Patent number: 5870686
    Abstract: An intelligent mobile product application control system capable of controlling product application by calculating control values on a per position basis from data that has traditionally been used to generate digital land area maps. The system includes a vehicle having coupled thereto at least one distributed network including at least one intelligent control module having a geographic raw data processor. The intelligent control module is responsive to raw geographic information data for controlling at least one actuator device in a manner that results in at least one predetermined product being applied to a predetermined geographic land area at variable rates determined by the raw geographic information data.
    Type: Grant
    Filed: August 21, 1997
    Date of Patent: February 9, 1999
    Assignee: Ag-Chem Equipment Co., Inc.
    Inventor: Robert J. Monson
  • Patent number: 5867405
    Abstract: A method and apparatus for simulating the design of a ferroelectric circuit uses a processor (501). The processor (501) executes a simulator (540) from memory (538) to exercise a ferroelectric model (544). The ferroelectric model (544) keeps track of turning points or extrema points (FIGS. 11-17) in a history data file (542). This history data in file (542) is then used with eqs. 3-11 herein to curve model between voltage/charge history points from the file (542) and a current operating voltage/charge point of the ferroelectric device. This curve modeling effectively and efficiently determines the charge stored in a ferroelectric capacitor (FIGS. 7 or 8) as voltage across the ferroelectric capacitor is varied over time and temperature. History data points are selectively removed from the data file (542) to maintain and enable time-efficient determination of charge (Q) in the ferroelectric device over time.
    Type: Grant
    Filed: March 1, 1996
    Date of Patent: February 2, 1999
    Assignee: Motorola, Inc.
    Inventors: Bo Jiang, Peter Zurcher, Robert E. Jones
  • Patent number: 5862364
    Abstract: Provided is a data processing system and a method for generating states of a model defined within a modelling application. The modelling application generates a state of the model based on the values of a number of input variables. A modification means alters the values of the input variables, and provides those altered values to the modelling application to cause a new state of the model to be generated. The modification means repeats the production of altered values such that a set of states of the model is generated. A display means produces a graphical representation of each state of the model in the set and displays the graphical representations on a display device.
    Type: Grant
    Filed: July 30, 1996
    Date of Patent: January 19, 1999
    Assignee: International Business Machines Corp.
    Inventor: Stephen James Paul Todd
  • Patent number: 5859785
    Abstract: A method and apparatus simulates the performance of a system from a user-specified description of the components in the system and the interconnections between the components. The user may specify the descriptions using a consistent syntax. Conservation relations are automatically generated using the description of the components, the interconnections between the components in the system, or both. The description provided by the user and the conservation requirements generated may be translated into models for use by a conventional simulator to complete the simulation. Alternately the description and the conservation relation may be formulated into a set of relations and solved using conventional methods, such as Modified Nodal or Sparce Tableau. System performance simulation information is then generated as desired by a user.
    Type: Grant
    Filed: November 20, 1997
    Date of Patent: January 12, 1999
    Assignee: Cadence Design Systems, Inc.
    Inventor: Kenneth S. Kundert
  • Patent number: 5857093
    Abstract: A method and apparatus for simulating a microprocessor-based system produces simulations which are fast and which are accurate in terms of timing information produced. The source code is first compiled so as to produce a first program for a target microprocessor. Timing information is then extracted from the first program. The source code is compiled so as to produce a second program for a simulation microprocessor. The timing information is inserted into the second program, either directly or indirectly by way of the original source code. The second program thus has the timing information embedded therein and available for use by the simulation microprocessor, such that an output based on the timing information may be generated during the execution of the second program. A simulator which simulates execution of a first program by a target microprocessor comprises a simulation microprocessor and a second program. The second program is derived from a same source code program as the first program.
    Type: Grant
    Filed: September 20, 1996
    Date of Patent: January 5, 1999
    Assignee: Allen-Bradley Company, LLC
    Inventor: Jonathan D. Bradford
  • Patent number: 5856926
    Abstract: An incremental logic synthesis system for generating an optimized circuit from given logic, wherein the optimized circuit satisfies a design constriction.
    Type: Grant
    Filed: February 7, 1996
    Date of Patent: January 5, 1999
    Assignees: Hitachi, Ltd., Hitachi Software Engineering Co., Ltd.
    Inventors: Kazuhiko Matsumoto, Takao Shinsha, Nobuyuki Hayashi, Hiromoto Sakaki, Miyako Tandai, Yasunori Yamada, Takahiro Nakata, Kaoru Moriwaki, Junji Koshishita
  • Patent number: 5852564
    Abstract: A computer system simulator concurrently models both processor operation and signal logic behavior and provides a high degree of user interaction and flexibility in the observation and control of signal values and memory contents during the execution of a simulation. During simulation, source equations for signals can be requested for display either through direct input of a signal name or through graphical interface with the simulation display. Signal equations can in this manner be traced back through several levels, which conveniently provides important information during the observation and modification of signal values. Memory areas may be associated with a processor and loaded with data to be executed by that processor during the simulation. The data can be displayed in both numerical and assembly code mnemonic form, and may also be modified by entering numbers or assembly instructions. The simulated processor execution may thus be interactively modified during the simulation.
    Type: Grant
    Filed: November 20, 1996
    Date of Patent: December 22, 1998
    Assignee: CPU Technology, Inc.
    Inventors: Edward C. King, Alan G. Smith
  • Patent number: 5850345
    Abstract: The present invention provides a synchronous distributed simulation apparatus having a simulation supervising device which supervises a simulation device, and the simulation device which performs a synchronous simulation under supervision of the simulation supervising device, in which the simulation supervising device comprises counting means for counting time in simulation, time width setting means for setting a time width of simulation for each time zone where facilities are operated in a manufacturing process which is an object of the simulation in accordance with the time counted by the counting means, and transmitting means for transmitting data showing the time width set by the time width setting means to the simulation device, and the simulation device comprises receiving means for receiving the data showing the time width transmitted by the transmitting means in the simulation supervising device, discrete-event simulation means for simulating the manufacturing process in which change of a state may be
    Type: Grant
    Filed: October 18, 1996
    Date of Patent: December 15, 1998
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Chan Soo Son
  • Patent number: 5847976
    Abstract: A method for determining a position and an orientation of a system that is mobile with respect to a transmitter of an electromagnetic field, the mobile system being placed in a carrier and being linked to a magnetic field sensor. The method including a first step of analytic modeling of the electromagnetic fields as a function of the coordinates of the sensor, a first field (B.sub.0) being created by the transmitter, a second field (B.sub.1) being created by the electrical currents induced in the carrier by the first field (B.sub.0), and a third field (B.sub.2) being created by the electrical currents induced in the mobile system by the first two fields (B.sub.0 +B.sub.1), the magnetic effect of each field (B.sub.0, B.sub.1, B.sub.2) being characterized independently of the effects of the other fields by the coefficients of a model thereof.
    Type: Grant
    Filed: May 29, 1996
    Date of Patent: December 8, 1998
    Assignee: Sextant Avionique
    Inventor: Jean-Louis Lescourret
  • Patent number: 5845124
    Abstract: The present invention is directed, in general, to network modeling, and more specifically, to systems and methods for generating and displaying a symbolic representation of a network model. The present invention provides a method of graphically displaying data on a display device of a processing system and a computer system employing the method. The processing system includes a memory for storing tasks, a processing circuit for executing ones of the tasks, and a display device. The display device, which is associated with the processing circuit, is operative to provide a display area that is accessible to executed ones of the tasks. The display area is capable of displaying a symbolic representation of a network model. The memory includes a network modeling task that is retrievable and executable by the processing circuit to create a set of associated data records representing network elements within the network model.
    Type: Grant
    Filed: May 1, 1996
    Date of Patent: December 1, 1998
    Assignee: NCR Corporation
    Inventor: Jeremy S. Berman
  • Patent number: 5844819
    Abstract: There is provided an apparatus for aiding mechanism design such that mechanism design is aided by performing simulations of mechanism operations, the apparatus comprising a section for generating mechanism operation simulation data in accordance with predetermined data relating to a mechanism operation of a subject to be verified, a section for generating a time chart of the mechanism operation of the subject to be verified in accordance with the generated mechanism operation simulation data, and a section for displaying the generated time chart on a screen.
    Type: Grant
    Filed: September 18, 1996
    Date of Patent: December 1, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tomohisa Fujinuma
  • Patent number: 5842003
    Abstract: A hardware message transfer control unit designated as the Auxiliary Message Arbitrator Unit (AMA) manages message transfers and transfer protocols in a network of sending and receiving digital hardware modules. Flexibility of network expansion to include software emulated digital modules to the hardware modules is provided in RAM circuitry at the message transfer control unit.
    Type: Grant
    Filed: March 26, 1997
    Date of Patent: November 24, 1998
    Assignee: Unisys Corporation
    Inventors: Richard Mike Holmes, Mark Jeffrey Tadman, Leon Arie Krantz
  • Patent number: 5838594
    Abstract: A finite element mesh generating method generates triangular meshes used in finite element method analysis. This finite element mesh generating method includes the steps of (a) inputting orthogonal meshes used in finite difference method and mesh joining conditions, (b) setting flags indicating candidates of lattice points which are to be deleted out of lattice points of the orthogonal meshes, based on the orthogonal meshes, (c) reducing a number of meshes by joining the lattice points having the set flag and lattice points adjacent thereto, based on the mesh joining conditions, and (d) successively generating triangular meshes by searching nodes formed by lattice points remaining on the meshes after joining the lattice points and generating oblique sides of rectangles which are formed by connecting the nodes.
    Type: Grant
    Filed: January 25, 1996
    Date of Patent: November 17, 1998
    Assignee: Fujitsu Limited
    Inventor: Shuichi Kojima
  • Patent number: 5838948
    Abstract: A system for simulation of target electronic systems combining interacting elements of hardware and executing software, in part by physical emulation means and in part by abstract software simulation. A processor emulator is coupled to a hardware simulator by a communications link. The processor emulator provides the functionality of the target microprocessor while the hardware simulator simulates additional target circuitry. The processor emulator is coupled to a memory containing the target program. Most computer instructions in the target program do not require interaction with the target circuitry simulated on the hardware simulator. However, when a computer instructions requires the interaction of the target microprocessor and the target circuitry, a communications link control the communication between the target microprocessor and the target circuitry. The various components of the system can be coupled together via a conventional computer network.
    Type: Grant
    Filed: December 1, 1995
    Date of Patent: November 17, 1998
    Assignee: Eagle Design Automation, Inc.
    Inventor: Geoffrey J. Bunza
  • Patent number: 5838949
    Abstract: A simulator interface unit receives simulation results associated with a particular set of result identifiers and generated by an electronic design simulator. For each such result identifier, a history file manager stores a simulation result corresponding to a simulation-time value change. The history file manager additionally stores each simulation result generated beyond a first result activity during the execution of simulation code associated with each simulation-time value. The history file manager maintains an internal-time value that indicates when each stored simulation result was generated during the execution of simulation code, relative to the generation of each other stored simulation result. The history file manager generates a time translation table that associates unique simulation-time values with internal-time values. A results data server, in conjunction with viewing and interface tools, selectively present simulation results in a simulation-time format or a sequence-time format.
    Type: Grant
    Filed: December 28, 1995
    Date of Patent: November 17, 1998
    Assignee: Design Acceleration Inc.
    Inventor: Jean Andre Hassoun
  • Patent number: 5838950
    Abstract: The host adapter integrated circuit is a one chip high performance bus master host adapter for (i) connecting a first bus having a specified protocol for transferring information over the first bus and a first data transfer speed to a second bus having a specified protocol for transferring information over the second bus and a second data transfer speed, and (ii) transferring information between the two buses. The host adapter integrated circuit, hereinafter host adapter, includes a novel reduced instruction set computing (RISC) processor, a first interface module circuit connectable to the first bus and coupled to the RISC processor, a second interface module circuit connectable to the second bus and coupled to the RISC processor, and a memory circuit means connected to the first interface module circuit and to the second interface module circuit and coupled to the RISC processor.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: November 17, 1998
    Assignee: Adaptec, Inc.
    Inventors: Byron Arlen Young, Paul von Stamwitz
  • Patent number: 5828979
    Abstract: A system and method for controlling the movement of plural freight trains through a multiple route railway system with improved efficiency and safety. Freight train movements are precisely monitored and orchestrated in accordance with a dynamic schedule that is determined through an evaluation of delivery requirements, coordination among all trains, speed restrictions and the effects of the track topography and train consist on train response to brake and power application.
    Type: Grant
    Filed: May 15, 1997
    Date of Patent: October 27, 1998
    Assignee: Harris Corporation
    Inventors: Alan L. Polivka, William L. Matheson