Abstract: A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Abstract: A data processing apparatus includes apparatus for modelling asynchronous logic circuits as at least two of circuit elements the functions of which are governed by a set of rules each defining a response to a given condition. For elements functioning as registers (x,b) a "copy" rule may be applied to at least one of them (x) with the associated response to the copy rule being the change of the output state of that register element (218,220) in response to a change of output state of a further register element (b) identified by the copy rule. A further "identify" rule (200-226) may be applied to pairs of the register elements (x,b), according to which rule copy rules are applied to each element of the pair (216-222) in respect of changes of output state of the other. The apparatus may be arranged to model a number of asynchronous logic circuits in a working memory area with interconnections between such circuits being established by use of the identify rule.

Abstract: Methods for implementing a portion of a user's logic design in a component such as a random access memory, a read-only memory, an arithmetic logic unit, a digital signal processor, a microprocessor, or the like which is associated with programmable logic array integrated circuitry are disclosed. A candidate portion of the user's logic is identified and its logic requirements are determined and compared to the logic capabilities of the auxiliary component. If the candidate logic portion can be implemented in the auxiliary component, that may then be done. Alternatively, additional analysis may be performed prior to implementation (e.g., to make sure that it is beneficial to implement this logic portion in the auxiliary component and/or to ascertain whether it would be more beneficial to implement some other portion of the logic in the auxiliary component).

Abstract: A system and method of pass through in a heterogeneous distributed database environment allows a client to specify syntax that is only understood and processed by a database instance of a back-end server even if it is not understood by an interface module. A hybrid pass through feature provides a combination of both a pass through mode and a native mode allowing statements to be passed through to the database instance or to be processed by the interface module. To accomplish this, a pass through session is established. The scope of the pass through session is defined by statements that establish and terminate the session. Rules determine whether dynamic statements are handled in pass through mode or in native mode based on whether the statements are within or outside of the scope of the pass through session. Input host variable support is provided to database instances that don't otherwise support host variables.

Abstract: A system and method is presented for generating a computer assisted design circuit net list descriptive of a semiconductor integrated circuit design based on mask patterns used during the formation of the semiconductor. Masking pattern data, stored in a library data base, is processed by a central processing unit into primitive elemental circuit data and interconnection data. Coordinate and other information included in the primitive and interconnection data is then simplified. The simplified data is then supplemented to account for data simplification. The supplemented data is further processed to generate a symbolic circuit layout and a primitive net list.

Abstract: The present invention relates to a display system for displaying a past track of the ship, the present position of the ship, and a future predicted track of the ship, A display system according to the present invention generates coordinate data representing a desired pattern based on the ship's speed and the ship's bearing in order to display a past track of the ship and a future predicted track of the ship.

Abstract: An emulation system is constituted with a plurality of FPGAs having on-chip integrated debugging facilities, distributively disposed on a plurality of circuit boards. Each FPGA's on-chip integrated debugging facilities include in particular, a scan register for outputting trace data, and comparison circuitry for generating inputs for a plurality of system triggers. Correspondingly, each board is provided with a plurality of trace memory for recording the trace data, and summing circuitry for generating partial sums for the triggers. The relative memory location within a clock cycle of trace data where the output of a LE will be recorded is predeterminable. Additionally, a system sync memory is provided for storing a plurality of sync patterns to facilitate reconstitution of trace data of a trace session.

Abstract: In an air traffic control system, an in-line, data cable interface is disclosed for air traffic control signals which provides data access for use by an external computer system while preventing the disruption of the existing air traffic control signals. The interface provides non-intrusive data access even when the conductors of the data cable interface are short circuited. An external computer system has an associated software program capable of compiling received signals from the in-line data cable interface together with signals from other data sources and displaying the signals in, upon instructions of the user, hexadecimal form, polar graphical form or table form or recording the data onto computer or floppy disk. The air traffic control data is compared with data from another source such as a noise detector to monitor aircraft noise.

Abstract: A computer aided design system converts system level timing constraints to the minimum number of path-based timing constraints necessary to represent the same timing constraints as the system level timing constraints. Using a data structure for each node of the circuit, signal arrival times and required arrival times for each node are generated for each high level timing constraint, and the worst slack time is identified for each node. Then, a node with a worst slack time is selected, the constraint associated with that worst slack time is identified, and then a worst case path from a start node of the identified constraint through the selected node to an end node of the identified constraint is determined. The start and required signal arrival times associated with the identified constraint's start and end nodes in the determined path are also identified.

Abstract: Method and device for modelling the variables relevant to a process as a function of other parameters describing or influencing the process, termed regressors, by means of multiple regression for the purpose of process identification, monitoring, analysis and control or regulation. The classical method of stepwise multiple regression is expanded by the introduction of the so-called collinearity cone into a recursive method yielding all "best" collinearity-free regression models. The method is completed by giving consideration to the regression errors and by restriction to the absolutely necessary matrix elements. Stable regression models of various sizes are thus produced with little expenditure of time. Further, either linear or nonlinear regression functions permit a more accurate process analysis or modelling. By automatic learning in the case of newly occurring combinations of regressive values, it is also possible to apply the process to process monitoring, control and regulation.

Abstract: A logic circuit generating method and apparatus generating logic circuits of a circuit system by minimizing the fan-out count of cells or cell macros constituting information specific to the circuit system. According to the method, a Boolean expression and the polarities of its input/output variables are input from a design master file of the apparatus. The Boolean expression is then transformed into a two-branch tree composed of nodes represented by the logical operators of that expression. In the two-branch tree, the nodes representing a parent and a child logical operator are converted into a single node, whereby a multiple-branch tree is generated. That is, a plurality of gates are connected to a single net, or signal line. A cell library is referenced so that cells are assigned initially to the multiple-branch tree thus obtained. The initial cell assignment is performed preferentially starting from the cell whose fan-out count is the largest.

Abstract: A starting device integrates an output signal of an acceleration sensor by a band-pass integrating means while restricting an upper limit of the output signal in a specified frequency range by an upper limit restricting means, and is provided with a comparing means for outputting a starting signal when the integrated value is larger than a predetermined threshold value. In this way, the starting device is certainly started by an acceleration waveform of collision that must start the device. Further, the device is not influenced by vibration components caused immediately after the beginning of collision with respect to a low-speed collision such as 8 mile/hour frontal collision that must not start the device.

Abstract: Method and device for control within a line network such as a tram line, of a number of rolling units in various line runnings, and a method for installation of said device. A number of passive position determination elements (9) such as transponders, arranged for radio scanning, are located at determined positions in the network. Control equipment (2) on board said rolling units is provided with devices (8) for scanning of the position determination elements (9) and with sensors (6) for measurement of distance travelled. The momentary unit position within the line network is determined by continuous measurement of distance travelled and by calibration of the thereby obtained position determination by scanning of successively passed position determination elements (9). Data on the design and topography of the line network is stored in a central equipment (1) and communication from the mobile units stating their positions is received in a data processing unit (4).

Abstract: A data processing apparatus includes a unit (60,68) for modelling a first asynchronous logic circuit as a plurality of circuit elements the functions of which are governed by a set of rules each defining a response to a given condition. For elements functioning as registers, units are provided to apply a constraint (for example an algebraic or Boolean relationship) linking the internal values or output states of two or more of the registers. In response to a change in the internal value or output state of one of the registers, the corresponding one of the internal value or output state of the or one of the other registers is modified to maintain validity of the constraint. Each of the registers has a pointer (VP) to a respective data value or constraint information held in storage (67).

Abstract: One or more of control bits (FIG. 7) are formed within a data processor (12) wherein the one or more control bits (FIG. 7) are programmable by the CPU (150) of the data processor (12). When the CPU (150) programs the one or more control bits (FIG. 7) to a first logic state, the one or more chip select control signals which are routed external to the data processor (12) are arbitrated with the external bus. Therefore, the processor (12) must have ownership of the external bus in order to drive the chip selects when operating in this mode of operation. When the CPU (150) programs the one or more control bits (FIG. 7) to a second logic state, the one or more chip select control signals which are routed external to the data processor (12) operate independently of the bus ownership. This ability to select between two modes of operation provides greater flexibility in board level configuration and design.

Abstract: The present invention provides a method (500), device (400), microprocessor (500) and microprocessor memory (400, 500, 600) for instantaneous preemption of packet-switched data from a user that has won contention for a channel and for transmitting on a time slot, by higher priority traffic type data or voice in a TDMA communication system having a central access manager and a plurality of subscriber units. Before transmitting a packet on an uplink channel, the subscriber unit first selects a time slot and contends for channel access on the time slot. Upon gaining access to the uplink channel, the subscriber unit begins transmitting segments of a data packet on the selected time slot, suspending transmission when a higher priority user gains access to the time slot and, where decoding fails, suspending transmission for the time slot. The subscriber unit continues to transmit on the selected time slot until the packet ends.

Abstract: A type definition ability in a graphical programming environment which enables a user to assign a name to a custom control that the user intends to use throughout one or more virtual instruments. The user can create a master or original of a control and use copies of that control in all subsequent virtual instruments. If a user subsequently needs to change that control, the user merely updates the single master control which was saved as a type definition. This has the effect of updating all other copies of that control to that of the changed master or original control. An auto-update feature is included which allows a user to choose between automatic updating of all type definition copies or merely indicating to the user which controls need to be updated. Strict type definitions are provided wherein virtually any user change made to a parameter of the original typedef, i.e. appearance, propagates throughout the remaining instances or copies where that type definition is used.

Abstract: For FPGAs and other logic devices using four-input function generators, several combinations of primitive functions are provided for mapping hardware descriptions of logic designs into the FPGAs or logic devices. Automatic tools using this library will reliably produce dense designs when implemented in coarse-grained architectures.

Abstract: An in-system programing/erasing/verifying structure for non-volatile programable logic devices includes a data input pin, a data output pin, an instruction register, a plurality of data registers including an ISP register, wherein said instruction register and said plurality of data registers are coupled in parallel between said data input pin and said data output pin, and a controller for synchronizing said instruction register and said plurality of data registers. The ISP register includes: an address field, a data field, and a status field. An ISP instruction need only be entered once to program/erase the entire device. Specifically, the address/data packets can be shifted back to back into the ISP register without inserting multiple instructions between each packet at the data input pin, thereby dramatically decreasing the time required to program/erase the entire device in comparison to known ISP methods. Furthermore, the invention provides an efficient method for providing the status (i.e.

Abstract: Select sets of a logic function corresponding to an output of a first logic circuit are determined. These select sets are used to obtain a second logic circuit, the logic function corresponding to the output of which is the same as the logic function corresponding to the output of the first logic circuit. A propagation delay through the second logic circuit may be smaller than a corresponding delay through the first logic circuit. Sometimes, such a smaller propagation delay through the second logic circuit results in the second logic circuit having a smaller critical path delay. The second logic circuit may therefore have a greater maximum operating speed than the first logic circuit.