Abstract: A data resampler for a data processing system for logically adjacent data samples is provided. The data resampler includes a memory subsystem for storing samples to be rendered, a digital differential analyzer (DDA) for generating an interpolation corner address for a sample to be rendered and which also generates a set of interpolation fractions. The resampler also includes a fetch unit, which receives the generated interpolation corner address and generates four source addresses of samples to be fetched from the memory subsystem. A number of memory units are included in the resampler. The first memory unit is a first in, first out FIFO memory, for holding the generated interpolation fractions and for permitting the DDA and fetch unit to continue to operate during memory read latency periods. The second memory unit is also a FIFO memory and is used to hold pixel data.

Abstract: Instructions in an execution pipeline of a SIMD machine are monitored, preferably in the instruction decode phase. Upon detecting a 1/x or 1/sqrt(x) reciprocal operation, portions of the data are forwarded to logic that implements the given instruction. The portions of the instruction that are forwarded include the data value of x and the target address (or register) to which to write the result. The logic generates an n-bit seed for iterative processing by an arithmetic unit, and eliminates a requirement to provide lookup tables in each SIMD processor.

Abstract: An on-screen display unit solves a problem of a conventional on-screen display unit. The conventional unit cannot implement a moving display of an image with a small amount hardware. The novel on-screen display unit includes a first memory for storing the image code of each of images to be displayed. A second memory stores font data of the images. A latch circuit stores information indicating one of a moving display ON mode and a moving display OFF mode. A line memory stores at least one horizontal line image. An image data generating unit generates image data to be stored in the line memory. A selector selects output data from the second memory when the latch circuit stores information indicating the moving display OFF mode and selects output data from the line memory when the latch circuit stores information indicating the moving display ON mode.

Abstract: A computer graphics system for rendering graphics primitives based upon primitive data received from a host computer through a graphics interface includes a plurality of geometry accelerators. A distributor divides the primitive data into chunks of primitive data and distributes the chunks to a current geometry accelerator recipient. A state controller is configured to store and resend selected primitive data to the geometry accelerators based upon whether one or more vertices of a graphics primitive are contained in more than one of the chunks of primitive data. Advantageously, this enables the computer graphics system to efficiently process primitive data while avoiding providing the geometry accelerators with an excessive amount of data than necessary for them to render the primitives.

Abstract: A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes an XY address for rendering the graphics primitives. A graphics processor, which includes a bypass logic circuit, enables the graphics processor to temporarily store display list commands in an internal storage device while previously fetched display list data is being processed. The bypass logic circuit allows the graphics processor to bypass the internal storage device and write fetched command directly to an execution unit in the graphics processor. By having the bypass capabilities, the graphics processor is able to optimize the internal storing of commands in the display list in the internal storage unit.

Abstract: A graphics controller circuit comprising a plurality of pipelines for performing a set of operations on a stream of input pixel data to generate at least a first operand and a second operand. A rasterop unit in the graphics controller circuit may receive the first operand and the second operand, and execute a raster operation using the first operand and the second operand to generate a set of display pixel data. The graphics controller circuit may further comprise a transparency unit for generating a write enable mask corresponding to the set of display pixel data. A display memory may selectively store or block the set of display pixel data according to the write enable mask. As the graphics controller generates display signals from the display data stored in display memory, a transparency operation may be performed.

Abstract: A window management mechanism allows a user to open a window as a drawer or, perhaps more appropriately named, a pop-up window. The drawer is an opened window that a user has dragged down to a drawer region at the bottom of the screen such that only the title bar or some drawer handle illustration is left showing. When the user does this, the window remains open but is kept offscreen. The user may momentarily pop the window back onto the screen by clicking on the window title bar or drawer handle, or by dragging the cursor into the window icon during a drag. The window stays onscreen as long as no other windows are selected. As soon as a user selects another window, or opens a file with a double click within the drawer, the window slides back offscreen. This allows the user to set up easy access windows. Another feature of a drawer window allows the user to open them during a drag. To do so, the user drags an object or the cursor into the drawer window that is desired to be opened.

Abstract: A multimedia terminal for adapting audio-video signals into a digital data network is provided. The terminal comprises a video decoder, a video encoder, a frame buffer, and a host processor coupled to the frame buffer. The frame buffer has a plurality of memory fields, a system time clock that is switchable from a free running clock to being locked to the analog video signals and a frame buffer logic control circuit which controls the flow of data in and out of the memory fields. The frame buffer is able to operate in two distinct modes.

Abstract: A software queue located in an offscreen portion of video memory is used as a large-capacity software queue for queuing messages to a graphics accelerator. Although the software queue is typically stored in a dynamic RAM (DRAM) memory, advantages of faster static RAM (SRAM) are achieved by shadowing some of the queuing information in SRAM. Usage of a large-capacity software queue in video DRAM memory and information shadowing in faster SRAM memory achieves an advantageous balance between throughput speed and queue size. The large-capacity of the software queue ensures that the queue is virtually never filled to capacity so that delays while awaiting free space in the queue are virtually never incurred. The capacity of the software queue is determined in software and is therefore adaptable to match a particular graphics application.

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory. The core logic chipset may cache a subset of the most recently used GART table entries to increase AGP performance when performing the address translation.

Abstract: The present invention relates to a programmable retargeter memory device which receives data being sent to addresses designated by the data and which retargets the data by replacing the addresses designated by the data with new addresses. The retargeter memory device of the present invention comprises an address memory and a data memory. The address memory comprises a plurality of address memory locations for storing retargeted addresses. The address memory is capable of being written to and read from to programmably alter the retargeted addresses stored therein and to output retargeted addresses therefrom. The data memory comprises a plurality of data memory locations for storing data associated with the retargeted addresses stored in the address memory and is capable of being written to and read from.

Abstract: A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes a XY address for rendering the graphics primitives. A graphics processor which includes an address tracking logic circuit tracks the rendering primitive to determine the minimum and maximum XY addresses of the rendered primitive. By tracking of the XY address, the graphics processor is able to internally cache only modified portions of the rendered primitive thereby improving the graphics processor's access cycle to the modified data. Accordingly, the graphics processor's memory bandwidth requirements is reduced.

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. A plurality of AGP memory-mapped status and control registers are stored in the computer system memory, and are used for status and control of AGP functions in the computer system.

Abstract: In an image display device, a ROM contains a plurality of image data indicative of the actions of an animal character. A RAM includes a plurality of action level registers each of which stores for each image data the state of inputs given to select and display the image data. The user gives a command corresponding to a respective image of an animal character to select and display the action of the animal character optionally. When a random number corresponding to the command is generated, image data which does not correspond to the input command can be displayed. If the generated random number has a particular value, the value of an action level register for the image data corresponding to the command is updated. Such operation is iterated and thus the value of the action level register is updated.

Abstract: A memory system for processing a digital video signal capable of accessing data in block units includes a detector circuit discriminating whether the memory system is in a reading/writing operation in one of an integer pel mode and a half pel mode. A controller circuit is coupled to the detector circuit and controls access of data in units of m.times.n bit block when the memory system is determined to operate in the integer mode by the detector circuit. The controller circuit controls access of data in units of (m+1).times.(n+1) bit block when the memory system is determined to operate in the half pel mode of a reading operation.

Abstract: A graphics processor for rasterizing graphics data using display list programming to a host computer system memory. The processor dynamically rasterizes the display list generated by a host processor to either graphics memory local to the graphics processor or to the host system memory. The graphics processor of the present invention includes a prefetch unit having instruction prefetch logic for prefetching and decoding next opcode instructions in a display list of instructions from system memory. Prefetching a next instruction eliminates steup time necessary to fetch subsequent opcode instructions after a first opcode instruction has been fetched. The next opcode instruction in a sequential display list of instructions is prefetched with parameter data associated with the first fetched opcode instructions to save the graphics processor extra instruction fetch cycle time necessary to fetch subsequent opcode instructions.

Abstract: A frame memory interface architecture which is easily adaptable to interface to any of a plurality of frame memory storage architectures. In the preferred embodiment, the present invention comprises an MPEG decoder system and method for decoding frames of a video sequence. The MPEG decoder includes various slave devices which access a single external memory, wherein these slave devices include reconstruction logic or motion compensation logic, a reference frame buffer, display logic, a prefetch buffer, and host bitstream logic, among others. Each of the slave devices is capable of storing or retrieving data to/from the memory according to different frame storage formats, such as a scan line format, a tiled format, and a skewed tile format, among others. The frame memory interface is easily re-configurable to each of these different formats, thus providing improved efficiency according to the present invention. The slave device then generates a request to the memory controller.

Abstract: A data processing apparatus includes a graphics display device for displaying a display frame comprising a plurality of display frame pixels. A sprite management system composes the display frame from a plurality of graphic sprites. Each graphic sprite comprises a plurality of sprite pixels and corresponding sprite pixel values. Each sprite has a specified depth relative to the other sprites. One of the sprites is designated to be a video sprite. This sprite is loaded with a chroma-key value. The sprite management system includes a data processing device connected to access a display frame composition buffer. The data processing device is programmed to write pixel values of individual sprites to the display frame composition buffer. This writing begins with the pixel values of the sprite having the greatest depth and proceeds with the pixel values of the remaining sprites in order of decreasing sprite depth.

Abstract: Various character strings are repeatedly displayed on a graphics display. For example, strings such as "file", "edit", "view" and "help" are commonly displayed on nearly every screen. This redundancy of displayed character strings is exploited using a string cache and string caching method. A string cache stores a database of strings along with the rendered forms of the strings. The string cache stores the strings in a rendered form which for particular character strings and attributes and characteristics of the strings. The string cache is stored and accessed local to a graphics accelerator so that a single string request across a system bus activates the display of the entire string, including a display of the selected attributes and characteristics.

Abstract: For the sake of elevating significantly user's flexibility in edits of video signals, the memory control device for video editors comprises a storage means for storing at least one or more of title data composed of video image data representing title signals and key data used for controlling the title signal; a first memory for storing video image data and which is provided with a data reading means for reading the video image data so as to be capable of displaying the data in the form of a video image; a second memory for storing a key data and which is provided with a video image controlling means for controlling a video image to be displayed on the basis of the key data read; a specifying means for specifying a memory into which is to be written the title data; and a writing means which reads the video image data and the key data of title data to write both the data read into the first memory and the second memory, respectively, in the case when the first memory is specified by the specifying means, while