Abstract: The present invention provides a method and apparatus for transferring a video image, to be resized, from a host processor to an accelerator chip of a display adapter such that the storage capacity of a memory device in the chip is greatly reduced. The video data is first divided into MxM arrays of data elements. Then, the arrays are transferred one row at a time. Each row is stored before being processed by the chip. Consequently, since these rows are much shorter than the lines of frames of data elements, the storage capacity of the chip's memory device is greatly reduced.

Abstract: Software, resident or a host computer, that is capable of parsing a data stream of multiple interleaved data signals into the individual data signals that are then ready for manipulation and further processing by the host computer.

Abstract: A system and method for reordering memory references for pixels to improved bandwidth and performance in texture mapping systems and other graphics systems by improving memory locality in conventional page-mode memory systems. Pixel memory references are received from a client graphics engine and placed in a pixel priority heap. The pixel priority heap reorders the pixel memory references so that references requiring a currently open page are, in general, processed before references that require page breaks. Reordered pixel memory references are transmitted to a memory controller for accessing memory.

Abstract: A Video Display FIFO includes a circular buffer and counters that allow the FIFO to properly recover from data alignment problems caused by FIFO underflow. A pair of counters store read and write pointers, which indicate the addresses of data read from and written into the buffer. Another counter stores a count of data in the buffer. Buffer underflow causes the count to go negative and the read pointer to advance ahead of the write pointer. Data written into the buffer while the total count is negative is not read out of the buffer. This allows alignment of the data to be restored.

Abstract: Methods and apparatus for generating image data are provided. A memory and a data processor are coupled with a system bus. In certain embodiments a data expanding apparatus is also coupled to the system bus and compressed data are transferred to the data expanding apparatus via the system bus and decompressed data are transferred therefrom to the memory without passing the compressed data through the data processor. Also in certain embodiments, an image data generation command string is transferred from the memory to an image data generation device via the system bus without passing the image data generation command string through the data processor.

Abstract: An image displaying apparatus includes a first line buffer for storing image data of an image to be displayed, a SRAM which is provided downstream of the first line buffer and in which the image data stored in the first line buffer are written, a second line buffer provided downstream of the SRAM for storing the image data read from the SRAM, a CRT provided downstream of the second line buffer, and a control circuit for controlling the operation of the first line buffer, the SRAM and the second line buffer so that time contention between write-in operation of the image data into the SRAM and read-out operation of the image data from the SRAM can be prevented, the memory capacity of the SRAM being greater than those of the first line buffer and the second line buffer. According to the thus constituted image displaying apparatus, it is possible to display images based on great quantity of image data at low cost.

Abstract: An apparatus and method for asynchronous compression of video information in a computer system. The apparatus includes data structures and functions for specifying synchronous or asynchronous compression of at least one uncompressed video frame, for specifying latency in the compression of the at least one uncompressed video frame, for initiating asynchronous compression of the at least one uncompressed video frame by a video compressor, for asynchronously retrieving from the video compressor at least one compressed video frame, for terminating asynchronous compression of the at least one uncompressed video frames by the video compressor, and for immediately retrieving from the video compressor the at least one compressed video frame when the at least one compressed video frame remains unretrieved after asynchronous compression is terminated.

Abstract: A system includes a requesting agent coupled to a system bus. The system bus includes an address bus, control lines for indicating a requested transfer type, a data bus, address bus arbitration control lines and data bus arbitration control lines. The system further includes a system bus arbiter coupled to the system bus for resolving competing requests for access to the address bus and for separately resolving competing requests for access to the data bus. A graphics controller for enabling the requesting agent to access a frame buffer has a memory, which may be a FIFO, responsive to a first control signal, for storing data received from a frame buffer. The memory is further responsive to a second control signal for supplying the stored data to the data bus. The graphics controller also includes a controller coupled to the system bus and to the memory means.

Abstract: A computer program product for presenting animated display objects to a user for selection on a graphical user interface of a data processing system is provided. A plurality of animated display objects are simultaneously displayed by a graphical user interface on a display device of the data processing system, thus allowing the user to view all of the plurality of animated display objects and make a selection of one of the plurality of animated display objects. One of the displayed animated display objects is selected, and a multimedia presentation associated with the selected animated display object is played.

Abstract: A graphics controller (IMC) which performs pointer-based and/or display list-based video refresh operations that enable screen refresh data to be assembled on a per window basis, thereby greatly increasing the performance of the graphical display. The graphics controller maintains pointers to various buffers in system memory comprising video or graphics display information. The graphics controller manipulates respective object information workspace memory areas corresponding to each object or window, wherein the workspace areas specify data types, color depths, 3D depth values, alpha blending information, screen position, etc. for the respective window or object on the screen. Each workspace area also includes static and dynamic pointers which point to the location in system memory where the pixel data for the respective window or object is stored.

Abstract: An image information processing apparatus includes a cross bar switch circuit receiving first image information which indicates a two-dimensional image and second image information which indicates three-dimensional computer graphics describing a three-dimensional object by approximation using a plurality of polygons, an arbitration circuit controlling a connection of the cross bar switch circuit according to a predetermined rule based on a synchronizing signal which is related to the first image information, and a memory unit having a first memory region and a second memory region which is different from the first memory region. The memory unit is capable of reading information from the second memory region during a time in which image information output from the cross bar switch circuit is written in the first memory region.

Abstract: A document-centered user interface architecture for a computer system employs parts as the fundamental building blocks of all documents. All data is stored in the system as a part, which is comprised of contents and an associated editor. The contents and the functionality of the editor are available to the user wherever the part is located, whether in a document, on a desktop or in a folder. Parts function as containers for other parts, thereby facilitating the compilation and editing of multimedia or compound documents.

Abstract: A graphics display subsystem providing internally timed time-varying properties of display attributes is provided. The graphics display subsystem comprises a display device for displaying consecutive image frames of pixels having a variable display property, and a circuit for transferring image frames to the display device. One or more pixels are selected when a display attribute associated with the one or more pixels is set in an attribute table. The circuit varies, during a selected time interval, the display property of the selected pixels being displayed on the display device. In preferred embodiments, the variable display property is either a stereo image display, an image brightness control, or an image-blending control.

Abstract: The content of a color designating register 3 that designates any color is compared with data preliminarily written to a main VRAM 4. The compared resultant data is stored in a sub-memory 2. In the case that display data is read, when data stored in the sub-memory 2 represents "match," color data stored in a palette 8 is then stored in a CRT-FIFO 5 through a switching portion 10, and the read operation to the main VRAM 4 for relevant pixel data is stopped. When data stored in the sub-memory 2 represents "miss-match," color data stored in the VRAM is then stored in a CRT-FIFO 5 through a switching portion 10.

Abstract: A computer graphics system includes a plurality of geometry accelerators for processing vertex data representative of graphics primitives and providing rendering data. The system includes a distributor responsive to a stream of vertex data for distributing to the geometry accelerators chunks of the vertex data for processing by the geometry accelerators to provide chunks of rendering data. The distributor generates an end of chunk bit indicative of the end of each of the chunks of vertex data. The system further includes a concentrator for receiving the chunks of rendering data from each of the geometry accelerators and for combining the chunks of rendering data into a stream of rendering data in response to end of chunk bits. The stream of rendering data and the stream of vertex data represent sequences of graphics primitives having the same order. A rasterizer generates pixel data representative of a graphics display in response to the stream of rendering data.

Abstract: A method and structure including four video decompression structures and eight memory banks are provided for decoding high definition television (HDTV) signal. In this HDTV decompression structure, the 1920.times.1080 pixel display space is divided into four vertical sections of 480.times.1080 pixels. Each memory bank stores the values of pixels in one non-overlapping group of 240.times.1080 pixels. Each decompression structure decodes a 480.times.1088-pixel picture area with access to up to two additional 240.times.1088-pixel picture areas. The video decompression structures decode the vertical sections in lock-step to avoid the problem of the same bank of memory being accessed by more than one video decompression structure. In one embodiment of the present invention, a macroblock fetch can cross 1-4 DRAM page boundaries. So, in order to maintain the lock-step relationship of the video decompression structures, each page mode access is limited to fetching only an 8.times.

Abstract: A display controller for a computer or the like stored display data in a tiled format in a display memory. Tile shape may be dynamically altered depending upon display mode (resolution, pixel depth, or the like) or other display factors. Tile shape (height versus width) may be optimized for different types of display (e.g., video, text, graphics, or the like). A display memory address conversion apparatus may receive pixel position data (e.g., from a BIT BLT engine or the like) and tile shape data and convert pixel position data to a tiled display memory address.

Abstract: An image rescaling method utilizing a parallel processor is provided. The computer-implemented method includes the steps of loading multiple word components into a processor in one machine instruction, each word component associated with a pixel of an image; rescaling the multiple word components in parallel; and packing the rescaled multiple word components into an image buffer in one machine instruction. Additionally, a second set of multiple word components may be processed concurrently with the processing of a first set of multiple word components.

Abstract: A video picture written in the bit map memory (4) is displayed in a predetermined area on the display screen (70) of the display device (7) within the computer main body (100). The masking memory (2) having a bit number equal to or less than the number of the pixels of the video picture to be inputted is provided separate from the bit map memory (4). When the pixel data of the video picture data has been inputted, the input pixel data is selectively written in the bit map memory (4) based on the contents of the masking memory (2). In displaying a compressed picture of the input video picture on the display screen, an oblique line generating algorithm is used.

Abstract: In a measurement instrument, a display processor system and method for efficiently building a display image on a bit-mapped liquid crystal display are provided. The display processor system contains a set of bit plane images corresponding to predetermined images such as figures, menus, axes for a graphical plot, and other commonly needed images. Because the bit plane images are already processed and defined, operating on the display image becomes a simplified, high-level operation in which the desired image is constructed according to a display operation sequence. Virtual trace bit plane images are also employed to accommodate incoming measurement values which are appended to measurement traces, thereby causing the measurement traces to change rapidly. Virtual bit planes skip the intermediate step of constructing an entire bit plane image so that the displayed image may be more rapidly updated with the changing measurement traces.