Patents Examined by V. Yevsikov
  • Patent number: 7445989
    Abstract: A method of manufacturing a semiconductor device that comprises the steps of: removing a second insulating film on a contact region of a first conductor; forming a second conductive film on the second insulating film; removing the second conductive film on the contact region of the first conductor to make the second conductive film into a second conductor; forming an interlayer insulating film (a third insulating film) covering the second conductor; forming a first hole in the interlayer insulating film on the contact region; and forming a conductive plug, which is electrically connected with the contact region, in the first hole.
    Type: Grant
    Filed: January 28, 2005
    Date of Patent: November 4, 2008
    Assignee: Fujitsu Limited
    Inventors: Taiji Ema, Toru Anezaki
  • Patent number: 7425505
    Abstract: The present invention provides improvements to the use of silyating agents in semiconductor processing. More particularly, the silyating agents may be provided in combination with a substantially non-flammable ether, so that the combination is substantially non-flammable. Additionally, the silyating agent may be utilized in vapor form, or applied in conjunction with the electromagnetic radiation. Each of these embodiments can enhance the usability of the silyating agent, i.e., by rendering the silyating agent more safe, more easily utilized in a variety of processing equipment and/or by enhancing the passivation efficacy/efficiency of the silyating agent.
    Type: Grant
    Filed: July 19, 2004
    Date of Patent: September 16, 2008
    Assignee: FSI International, Inc.
    Inventors: Philip G. Clark, Kurt Karl Christenson, Brent D. Schwab
  • Patent number: 7413972
    Abstract: A method of forming a metal line in a semiconductor device using a fluorine doped silica glass (FSG) insulation layer. The method includes forming a lower metal layer on a insulation layer on a semiconductor substrate, forming a metal oxide layer on a sidewall of the lower metal layer, forming a barrier insulation layer covering the lower metal layer and metal oxide layer, forming an FSG insulation layer on the barrier insulation layer, forming a via contact that penetrates the FSG insulation layer so as to connect to the lower metal layer, and forming an upper metal layer electrically connected to the via contact.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: August 19, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Hee-Dae Kim
  • Patent number: 7371664
    Abstract: The present invention relates to a process for thinning a semiconductor wafer. Two surfaces of the wafer separately form a surface-bond glue (layer) and a surface protective glue (layer). The thinning process is applied to the wafer before forming the surface protective glue. Once the baking and drying process is applied to the surface-bond glue and the surface protective glue it then cuts the wafer. Finally, it dissolves the lower solubility of the surface protective glue to obtain the finished goods. The necessity of the selection of the wafer may serve to maintain quality standards. The wafer thinning process of the present invention is suitable for the extremely thin wafer. Thus, it reduces the production cost.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: May 13, 2008
    Assignee: Grace Semiconductor Manufacturing Corporation
    Inventor: Nan-Hsiung Tsai
  • Patent number: 7358112
    Abstract: A method of growing a p-type nitride semiconductor material having magnesium as a p-type dopant by molecular beam epitaxy (MBE), comprises supplying ammonia gas, gallium and magnesium to an MBE growth chamber containing a substrate so as to grow a p-type nitride semiconductor material over the substrate. Magnesium is supplied to the growth chamber at a beam equivalent pressure of at least 1 10-9 mbar, and preferably in the range from 1 10-9 mbar to 1 10-7 mbar during the growth process. This provides p-type GaN that has a high concentration of free charge carriers and eliminates the need to activate the magnesium dopant atoms by annealing or irradiating the material.
    Type: Grant
    Filed: June 13, 2002
    Date of Patent: April 15, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Jennifer Mary Barnes, Valerie Bousquet, Stewart Edward Hooper, Jonathan Heffernan
  • Patent number: 7348270
    Abstract: A method for forming interconnects onto attachment points of a wafer includes the steps of providing a mold with a plurality of cavities having a predetermined shape, depositing a release agent on surfaces of the cavities, filling the cavities with an interconnect material to form the interconnects, removing the release agent from the mold, and attaching the interconnects to the attachment points of the wafer. An adhesive layer can optionally be deposited in addition to the release layer. The adhesive layer can be used, for example, to bond the chip to a package.
    Type: Grant
    Filed: January 22, 2007
    Date of Patent: March 25, 2008
    Assignee: International Business Machines Corporation
    Inventors: David H. Danovitch, Mukta G. Farooq, Peter A. Gruber, John U. Knickerbocker, George R. Proto, Da-Yuan Shih
  • Patent number: 7344987
    Abstract: The present invention relates to a method for performing chemical mechanical polishing. A high down-force step is performed. A low down-force step is performed. At least one of the down-force steps is modified, based on if one of the down-force steps exceeds an acceptable tolerance associated therewith. Other systems and methods are also disclosed.
    Type: Grant
    Filed: June 2, 2006
    Date of Patent: March 18, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Yaojian Leng, Nilesh Shantaram Doke, Stanley Monroe Smith
  • Patent number: 7335586
    Abstract: A method for sealing a porous dielectric layer atop a substrate, wherein the dielectric layer is patterned to form at least a trench and at least a via, comprises applying a first plasma to a surface of the dielectric layer to silanolize the surface, treating the surface of the dielectric layer with a silazane to form a monolayer of silane molecules on the surface, and applying a second plasma to the surface of the dielectric layer to induce a polymerization of at least a portion of the silane molecules. The polymerized silane molecules form a cross-linked matrix that builds over a substantial portion of the surface of the dielectric layer and seals at least some of the exposed pores.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: February 26, 2008
    Assignee: Intel Corporation
    Inventors: Vijayakumar S. RamachandraRao, Boyan Boyanov, Grant Kloster, Hyun-Mog Park
  • Patent number: 7335587
    Abstract: A method for forming a semiconductor device is disclosed wherein atomic layer deposition (ALD) precursor species and/or by-product absorbed by an ILD are outgassed and/or neutralized prior to subsequently patterning the semiconductor device, thereby improving the ability to accurately define subsequently formed interconnect structures in the ILD.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: February 26, 2008
    Assignee: Intel Corporation
    Inventors: Steven W. Johnston, Kevin P. O'Brien, Sridhar Balakrishnan
  • Patent number: 7329917
    Abstract: The present teachings describe a container capacitor that utilizes an etchant permeable lower electrode for the formation of single or double-sided capacitors without excessive etching back of the periphery of the use of sacrificial spacers. The present teachings further describe a method of forming at least one capacitor structure on a substrate. For example, the method comprises forming at least one recess in the substrate, depositing a first conductive layer on the substrate so as to overlie the at least one recess, and defining at least one lower electrode within the at least one recess formed in the substrate by removing at least a portion of the first conductive layer. The method further comprises diffusing an etchant through the at least one lower electrode so as to remove at least a portion of the substrate to thereby at least partially isolate the at least one lower electrode.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: February 12, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Robert D. Patraw, Michael A. Walker
  • Patent number: 7326632
    Abstract: A method for fabricating metal wirings of a semiconductor including forming an etch stop layer on a semiconductor substrate, and forming an inter metal dielectric on the etch stop layer. The method also includes forming a via hole in the inter metal dielectric so as to expose the etch stop layer, and forming a trench on the inter metal dielectric so as to expose the via hole. The method further includes removing the etch stop layer exposed through the via hole, wet etching an inner wall of the trench, and forming a metal wiring inside the via hole and the trench.
    Type: Grant
    Filed: January 3, 2005
    Date of Patent: February 5, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jea-Hee Kim
  • Patent number: 7314837
    Abstract: A method is disclosed for removing liquids from a semiconductor substrate by contacting the liquid on the substrate with a liquid which attracts the liquid on the substrate, separating the liquids from the substrate, and inducing a phase transition in a layer on the substrate. In particular, the method is applicable to removing water from a water-containing layer on the substrate by contacting the layer with a hygroscopic liquid. Trenches on a substrate can be isolated by filling the trenches with a water-containing gel formed by reacting silane and hydrogen peroxide. The gel is contacted with sulfuric acid to remove a portion of the water from the gel before annealing to form silica in the trenches. Unlike filled trenches formed by conventional technology, there are no voids in the bottom of the trenches. The method is also applicable to forming dielectric layers which cover metal lines, low-dielectric layers, and interlayer dielectric layers.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: January 1, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Li Li, Weimin Li
  • Patent number: 7312153
    Abstract: A method is described for treating a wafer having at least a surface layer of semiconductor material, with the surface of this surface layer having undergone a chemical-mechanical polishing step followed by an RCA cleaning step. After the polishing step and prior to the RCA cleaning step, the method includes an intermediate step of cleaning the surface of the surface layer of semiconductor material using an SC1 solution under concentration and temperature conditions that allow the emergence of defects in the surface layer (curve B) to be reduced compared with a similar surface layer which has not undergone such an intermediate cleaning step (curve A).
    Type: Grant
    Filed: October 20, 2005
    Date of Patent: December 25, 2007
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Stéphane Coletti, Véronique Duquennoy-Pont
  • Patent number: 7306988
    Abstract: Methods of making memory devices/cells are disclosed. A memory cell contains first and second electrode layers and a controllably conductive media therebetween. The controllably conductive media contains a copper sulfide-containing passive layer and active layer containing a Cu-doped tantalum oxide and/or titanium oxide layer. Methods of using the memory devices/cells, and devices such as computers containing the memory devices/cells are also disclosed.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: December 11, 2007
    Assignees: Advanced Micro Devices, Inc., Spansion LLC
    Inventors: Steven C. Avanzino, Wen Yu
  • Patent number: 7307027
    Abstract: A method of forming a dielectric between memory cells in a device includes forming multiple memory cells, where a gap is formed between each of the multiple memory cells. The method further includes performing a high density plasma deposition (HDP) process to fill at least a portion of the gap between each of the multiple memory cells with a dielectric material.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: December 11, 2007
    Assignees: Advanced Micro Devices, Inc., Spansion LLC
    Inventors: Minh Van Ngo, Alexander Nickel, Hieu Pham, Jean Yang, Hirokazu Tokuno, Weidong Qian
  • Patent number: 7300886
    Abstract: A method of manufacturing a memory device includes forming a first dielectric layer over a substrate and forming a charge storage element over the first dielectric layer. The method also includes forming a second dielectric layer over the charge storage element and forming a control gate over the second dielectric layer. The method further includes depositing an interlayer dielectric over the control gate at a high temperature.
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: November 27, 2007
    Assignees: Spansion LLC, Advanced Micro Devices, Inc.
    Inventors: Minh Van Ngo, Ning Cheng, Wenmei Li, Angela T. Hui, Pei-Yuan Gao, Robert A. Huertas
  • Patent number: 7297636
    Abstract: Methods for fabricating devices having small feature sizes are provided. In an exemplary embodiment, a method comprises forming a patterned first mask layer overlying a subject material layer and isotropically etching the patterned first mask layer. A second masking layer is deposited overlying the patterned first mask layer and the isotropically-etched patterned first mask layer is exposed. The isotropically-etched patterned first mask layer is removed and the subject material layer is etched to form a feature therein.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: November 20, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Doug H. Lee, Andreas Knorr
  • Patent number: 7294581
    Abstract: Embodiments of methods for fabricating a spacer structure on a semiconductor substrate are provided herein. In one embodiment, a method for fabricating a spacer structure on a semiconductor substrate includes providing a substrate containing a base structure over which the spacer structure is to be formed. The spacer structure may be formed over the base structure by depositing a first layer comprising silicon nitride on the base structure, depositing a second layer comprising a silicon-based dielectric material on the first layer, and depositing a third layer comprising silicon nitride on the second layer. The first, second, and third layers are deposited in a single processing reactor.
    Type: Grant
    Filed: October 17, 2005
    Date of Patent: November 13, 2007
    Assignee: Applied Materials, Inc.
    Inventors: R. Suryanarayanan Iyer, Sanjeev Tandon
  • Patent number: 7291566
    Abstract: In order to mitigate erosion of exposed processing elements in a processing system by the process and any subsequent contamination of the substrate in the processing system, processing elements exposed to the process are coated with a protective barrier. The protective barrier comprises a protective layer that is resistant to erosion by the plasma, and a bonding layer that improves the adhesion of the protective layer to the processing element to mitigate possible process contamination by failure of the protective layer.
    Type: Grant
    Filed: March 18, 2004
    Date of Patent: November 6, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Gary Escher, Mark A. Allen
  • Patent number: 7288463
    Abstract: Conformal dielectric deposition processes supplemented with a deposited expansion material can fill high aspect ratio narrow width gaps with significantly reduced incidence of voids or weak spots. The technique can also be used generally to form composites, such as for the densification of any substrate having open spaces or gaps to be filled without the incidence of voids or seams.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: October 30, 2007
    Assignee: Novellus Systems, Inc.
    Inventor: George D. Papasouliotis