Abstract: A method of forming a contact hole of a semiconductor device, the method comprising: forming a gate line and a source/drain region in a substrate; depositing an etch stopper layer on the substrate; depositing a first interlayer dielectric layer on the etch stopper layer and flattening the first interlayer dielectric layer exposing a portion of the etch stopper layer; removing the exposed portion of the etch stopper layer; forming a gate protective layer on the gate line; depositing a second interlayer dielectric layer on the substrate; and etching the second interlayer dielectric layer to form a first contact hole on the gate line and etching the second interlayer dielectric layer, the first interlayer dielectric layer, and the etch stopper layer to form a second contact hole on the source/drain region, wherein the gate protective layer protects the gate line during the formation of the first and second contact holes.

Abstract: A memory cell, array and device include an active area formed in a substrate with a vertical transistor including a first end disposed over a first portion of the active area. The vertical transistor is formed as an epitaxial post on the substrate surface, extends from the surface of the substrate, and includes a gate formed around a perimeter of the epitaxial post. A capacitor is formed on the vertical transistor and a buried digit line vertically couples to a second portion of the active area. An electronic system and method for forming a memory cell are also disclosed.

Abstract: Disclosed herein are a CMP slurry composition with high-planarity and a CMP process for polishing a dielectric film using the same. More specifically, a CMP slurry composition with high-planarity includes a carbon compound having tens of thousands of carboxyl groups and having a molecular weight ranging from hundreds of thousands to millions, an abrasive, and water. A CMP process for polishing a dielectric film utilizes the disclosed slurry composition. The slurry composition enables complete and overall planarization of the dielectric film by polishing the part of the film having a higher step difference through CMP process. Accordingly, the disclosed slurry composition is useful for the CMP process of all semiconductor devices including those having ultrafine patterns.

Abstract: A method including forming a hard mask and an etch stop layer over a sacrificial material patterned as a gate electrode, wherein a material for the hard mask and a material for the etch stop layer are selected to have a similar stress property; removing the material for the hard mask and the material for the etch stop layer sufficient to expose the sacrificial material; replacing the sacrificial material with another material. A system including a computing device including a microprocessor, the microprocessor including a plurality of transistor devices, at least one of the plurality of transistor devices including a gate electrode formed on a substrate surface; a discontinuous etch stop layer conformally formed on the substrate surface and adjacent side wall surfaces of the gate electrode; and a dielectric material conformally formed over the etch stop layer.

Abstract: An inventive semiconductor device includes: a lower interlayer dielectric film provided on a substrate; a lower interconnect made up of a lower barrier metal layer formed along a wall surface of a lower interconnect groove in the lower interlayer dielectric film, and a copper film; and an upper plug and an upper interconnect. The upper plug passes through a silicon nitride film and comes into contact with the copper film of the lower interconnect. The lower interconnect is provided with a large number of convex portions buried in concave portions of the lower interconnect groove. Thus, voids in the lower interconnect are also gettered by the convex portions. Accordingly, the concentration of voids in the contact area between the lower interconnect and the upper plug is relieved, and an increase in contact resistance is suppressed.

Abstract: A method for fabricating a metal line in a semiconductor device is provided. The method includes: forming an inter-layer insulation layer on a substrate; forming a contact hole by etching the inter-layer insulation layer; forming a metal layer on the inter-layer insulation layer and the contact hole; etching a portion of the metal layer through performing a first etching process; and etching a remaining portion of the metal layer through performing a second etching process until the surface of the inter-layer insulation layer is exposed and a bottom portion of the metal line is sloped.

Abstract: For forming stacked capacitors, an opening is formed through at least one semiconductor material. A lower electrode material is patterned within the opening to form a plurality of lower electrodes within the opening. The stacked capacitors are formed with the lower electrodes within the opening by depositing a capacitor dielectric and an upper electrode within the opening. With such a relatively large opening, a capacitor dielectric of the stacked capacitors is deposited with a large thickness for improving reliability of the stacked capacitors.

Abstract: A composite structure is disclosed that includes a support wafer and a layered structure on the support wafer. The layered structure includes at least one layer of a monocrystalline material and at least one layer of a dielectric material. In addition, the layered structure materials and the thickness of each layer are chosen such that the thermal impedance between ambient temperature and 600° K of the composite structure is a value that is no greater than about 1.3 times the thermal impedance of a monocrystalline bulk SiC wafer having the same dimensions as the composite structure. The composite structure provides sufficient heat dissipation properties for manufacturing optical, electronic, or optoelectronic components.

Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.

Abstract: A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A sidewall spacer (156) is formed against an edge (137) of a layer of bottom electrode/copper diffusion barrier material (136), an edge (151) of a layer of capacitor dielectric material (150) and at least some of an edge (153) of a layer of top electrode material. The sidewall spacer (156) is dielectric or non-conductive and mitigates “shorting” currents that can develop between the plates as a result of copper diffusion. Bottom electrode diffusion barrier material (136) mitigates copper diffusion and/or copper drift, thereby reducing the likelihood of premature device failure.

Abstract: A manufacturing method of a semiconductor device disclosed herein, comprises: forming a first member to be patterned on a semiconductor substrate; patterning the first member to be patterned to form a plurality of parallel linear patterns and a connecting portion which connects the linear patterns on at least one end side of the linear patterns; and etching a region between the linear patterns and the connecting portion to separate the linear patterns and the connecting portion.

Abstract: A method for planarizing a semiconductor structure is disclosed. A semiconductor substrate having a first area in which one or more trenches are formed in a first pattern density, and a second area in which one or more trenches are formed in a second pattern density lower than the first pattern density, is provided. A first dielectric layer is formed above the semiconductor for covering the trenches in the first and second areas. A first chemical mechanical polishing is performed on the first dielectric layer using a predetermined type of slurry for reducing a thickness thereof. The first dielectric layer is then rinsed. A second chemical mechanical polishing is performed on the first dielectric layer using the predetermined type of slurry for further removing the first dielectric layer outside the trenches, thereby reducing a step height variation between surfaces of the first and second areas.

Abstract: The invention encompasses a method of forming a silicon nitride layer. A substrate is provided which comprises a first mass and a second mass. The first mass comprises silicon and the second mass comprises silicon oxide. A sacrificial layer is formed over the first mass. While the sacrificial layer is over the first mass, a nitrogen-containing material is formed across the second mass. After the nitrogen-containing material is formed, the sacrificial layer is removed. Subsequently, a silicon nitride layer is formed to extend across the first and second masses, with the silicon nitride layer being over the nitrogen-containing material. Also, a conductivity-enhancing dopant is provided within the first mass. The invention also pertains to methods of forming capacitor constructions.

Abstract: A method for chemical mechanical polishing of mirror structures. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method includes forming a first dielectric layer overlying the semiconductor substrate and forming an aluminum layer overlying the first dielectric layer, the aluminum layer having an upper surface with a predetermined roughness of greater than 20 Angstroms RMS. The method also includes processing regions overlying the upper surface of the aluminum layer using a touch polishing process to reduce a surface roughness of the upper surface of aluminum layer to less than 5 Angstroms to form a mirror surface on the aluminum layer. Preferably, a protective layer is formed overlying the mirror surface on the aluminum layer.

Abstract: In a storage electrode of a semiconductor device, and a method of forming the same, the storage electrode includes an outer cylinder including a first outer cylindrical portion having a first outer diameter, and a second outer cylindrical portion that is formed on the first outer cylindrical portion and having a second outer diameter, which is less than the first outer diameter, the first and second outer cylindrical portions having substantially equal inner diameters, and an inner cylinder formed on inner surfaces of the outer cylinder.

Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

Abstract: A method for forming a semiconductor device includes placing a Si substrate and an Sc2O3 powder source in an oxide chamber, and vaporizing the Sc2O3 powder source in the oxide chamber so as to form a single crystal Sc2O3 film on the Si substrate through electron beam evaporation techniques.

Abstract: A polymer spacer material may increase the dimensions of the patterned photoresist that is used as a mask to etch the layers below the photoresist, which in turn translates into smaller dimensions etched into the underlying materials. This allows for the formation of integrated circuits having smaller features, smaller overall size, and greater density of features. In particular, the use of a polymer spacer material allows for the formation of contacts within flash memory cells having decreased dimensions so that higher density flash memory cells may be created without causing shorts between contacts or shorts due to misalignment of the contacts. Additionally, the use of the polymer spacer material extends the use of photolithography technologies that are used to form the patterns into the photoresists.

Abstract: A method of fabricating an MIM capacitor is provided, by which higher capacitance can be secured per unit volume or area by forming a dual-stack type capacitor to increase an effective area of the capacitor. The method includes patterning a first metal layer, forming a planarized second insulating layer having a trench exposing a portion of the patterned first metal layer, forming a second metal layer within the trench, forming a first dielectric layer on the second metal layer, forming first via holes exposing the patterned first metal layer, forming first plugs filling the trench and first via holes, forming a third metal layer thereover, forming a second dielectric layer on the third metal layer, forming a patterned fourth metal layer on the second dielectric layer, patterning the second dielectric layer and the third metal layer, forming a planarized third insulating layer having second via holes therein, and forming a patterned fifth metal layer on the third insulating layer.

Abstract: An integrated circuit inductance and the fabrication method thereof are disclosed. The manufacture process provided by the present invention fabricates an integrated circuit inductance having a simple production process, low cost, a near equal loop size and good performance, due to making the order of the planarization processes of the inductance loops substantially perpendicular to the wafer and the direction of the current of the inductance substantially in parallel with the wafer, by way of the manufacture process of the plugs and the conductive wires of the integrated-circuit process.