Abstract: A composite turbine rotor blade that uses the high heat resistance capability of a ceramic material along with the high strength capability of a high strength metallic material. A main body or insert piece with a leading edge, a trailing edge and a blade tip is made from a single piece of CMC, Carbon/Carbon or high temperature resistant metallic material such as Columbium or Molybdenum. A pressure side wall piece and a suction side wall piece both made of the metallic material that is bonded together to sandwich in-between the insert piece. The insert piece includes a number of cross-over holes in which locking pins pass through from one of the two metallic pieces and form bond surfaces to bond the two metallic pieces together with the insert piece sandwiched in-between. The two metallic pieces each include a serpentine flow cooling circuit to provide cooling air flow form the metallic pieces.

Abstract: A method of fabricating a semiconductor device in which a plurality of conductive lines having a fine pitch and a uniform thickness can be formed is provided. The method includes forming a plurality of first conductive patterns in a insulation layer as closed curves, forming a plurality of mask patterns on the insulation layer, the mask patterns exposing end portions of each of the first conductive patterns, and forming a plurality of second conductive patterns in the insulation layer as lines by removing the end portions of each of the first conductive patterns.

Abstract: An isolation oxide film whose upper surface is higher than a surface of a substrate is formed in the substrate. A silicon oxide film is formed on the substrate between the isolation oxide films. A self-aligned polysilicon film is formed on the silicon oxide film between the isolation oxide films. After forming a resist pattern covering the peripheral circuitry, the isolation oxide films in the memory cell are etched by a predetermined thickness. An ONO film is formed on the entire surface of the substrate, a second resist pattern covering the memory cell is formed. Then, the ONO film, the polysilicon film 8 and the silicon oxide film 7 are removed from the peripheral circuitry.

Abstract: A phase change memory device and a method of manufacture are provided. The phase change memory device includes a phase change layer electrically coupled to a top electrode and a bottom electrode, the phase change layer comprising a phase change material. A mask layer is formed overlying the phase change layer. A first sealing layer is formed overlying the mask layer, and a second sealing layer is formed overlying the first sealing layer.

Abstract: Transistors (21, 41) employing floating buried layers (BL) (72) may exhibit transient breakdown voltage (BVdss)TR significantly less than (BVdss)DC. It is found that this occurs because the floating BL (72) fails to rapidly follow the applied transient, causing the local electric field within the device to temporarily exceed avalanche conditions. (BVdss)TR of such transistors (69. 69?) can be improved to equal or exceed (BVdss)DC by including a charge pump capacitance (94, 94?) coupling the floating BL (72) to whichever high-side terminal (28, 47) receives the transient. The charge pump capacitance (94, 94?) may be external to the transistor (69, 69?), may be formed on the device surface (71) or, may be formed internally to the transistor (69-3, 69?-3) using a dielectric deep trench isolation wall (100) separating DC isolated sinker regions (86, 88) extending to the BL (72). The improvement is particularly useful for LDMOS devices.

Abstract: A semiconductor device, such as a PMOS or NMOS device, having localized stressors is provided. Recesses are formed on opposing sides of a gate electrode. A stress-inducing region is formed along a bottom of the recess, and a stressed layer is formed over the stress-inducing region. By having a stress-inducing region with a larger lattice structure than the stressed layer, a tensile strain may be created in a channel region of the semiconductor device and may be suitable for an NMOS device. By having a stress-inducing region with a smaller lattice structure than the stressed layer, a compressive strain may be created in the channel region of the semiconductor device and may be suitable for a PMOS device. Embodiments may be applied to various types of substrates and semiconductor devices, such as planar transistors and finFETs.

Abstract: A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film. A dummy via or an insulating slit is formed on/in the upper interconnect near the via.

Abstract: A method for forming wavelength-conversion LED encapsulant structure includes forming an LED encapsulant structure body, forming a layer of a wavelength-conversion material on a first surface, disposing the first surface to cause the wavelength-conversion material to be in contact with a surface region of the LED encapsulant structure body, applying a pressure between the first surface and the surface region of the LED encapsulant structure body, and causing at least a portion of the wavelength-conversion material to be at least partially embedded in the surface region of the LED encapsulant structure body.

Abstract: An acoustical vibration dampening system for a rotatable blade comprises at least one section of a rotatable blade and a layer of acoustic damping material coupled to a portion of the at least one section of a rotatable blade. A fan blade comprises a first structural section of a fan blade, a second structural section of the fan blade, and a layer of acoustic damping material provided between the first structural section and the second structural section of the fan blade. A method of making a fan blade with acoustic damping comprises forming at least two sections of a fan blade, and disposing an acoustical vibration dampener between the at least two sections of the fan blade.

Abstract: Conventional “on-chip” or monolithically integrated thermocouples are very mechanically sensitive and are expensive to manufacture. Here, however, thermocouples are provided that employ different thicknesses of thermal insulators to help create thermal differentials within an integrated circuit. By using these thermal insulators, standard manufacturing processes can be used to lower cost, and the mechanical sensitivity of the thermocouple is greatly decreased. Additionally, other features (which can be included through the use of standard manufacturing processes) to help trap and dissipate heat appropriately.

Abstract: A method for manufacturing a light emitting device according to an embodiment of the present invention includes preparing a growth substrate; selectively forming a projection pattern on the growth substrate; forming a first conductive type semiconductor layer on the growth substrate and the projection pattern; forming an active layer on the first conductive type semiconductor layer; forming a second conductive type semiconductor layer on the active layer; and executing an isolation etching for selectively removing the first conductive type semiconductor layer, the active layer, and the second conductive type semiconductor layer including the projection pattern.

Abstract: A device made of single-crystal silicon having a first side, a second side which is situated opposite to the first side, and a third side which extends from the first side to the second side, the first side and the second side each extending in a 100 plane of the single-crystal silicon, the third side extending in a first area in a 111 plane of the single-crystal silicon. The third side extends in a second area in a 110 plane of the single-crystal silicon. Furthermore, a production method for producing a device made of single-crystal silicon is described.

Abstract: Circuits and methods for providing an SRAM or CAM bit cell. In one embodiment, a bit cell portion with thicker gate oxides in the storage cell transistors, and thinner gate oxides in a read port section having transistors are disclosed. The use of the thick gate oxides in the storage cell transistors provides a stable storage of data and lower standby leakage current. The use of the thinner gate oxides in the read port transistors provides fast read accesses and allows a lower Vcc,min in the read port. The methods used to form the dual gate oxide thickness SRAM cells have process steps compatible with the existing semiconductor manufacturing processes. Embodiments using high k gate dielectrics, dual gate dielectric materials in a single bit cell, and using finFET and planar devices in a bit cell are described. Methods for forming the structures are disclosed.

Abstract: A blade arrangement (22) comprises an aerofoil (26) and a mounting support (28) to mount the blade arrangement to a disc. The aerofoil (26) is supported on the mounting support (28). The aerofoil (26) comprises a plurality of elongate aerofoil portions (34) arranged adjacent one another to provide the aerofoil.

Abstract: A compound semiconductor device includes a carrier transit layer including GaN formed over a substrate; a carrier supply layer including GaN formed over the carrier transit layer; a source electrode and a drain electrode formed over the carrier supply layer; a first compound semiconductor layer including N in which a first opening is formed and that is located between the source electrode and the drain electrode over the carrier supply layer; a gate electrode extending from within the first opening to above the first compound semiconductor layer; and an insulator layer having a second opening that is smaller than the first opening, and insulating the gate electrode and the first compound semiconductor layer within the first opening. The gate electrode extends from within the second opening to above the first compound semiconductor layer.

Abstract: Disclosed is a semiconductor device comprising: a semiconductor substrate in which an integrated circuit is formed; a first resin film provided over the semiconductor substrate; a second resin film provided over an upper surface of the first resin film except at least a peripheral portion of the first resin film; and a thin film inductor provided over the second resin film.

Abstract: The present invention discloses pixel structures and fabrication methods thereof. The pixel includes a thin film transistor forming at a thin film transistor region and a storage capacitor forming at a pixel electrode region. The method includes: forming a gate conduction layer on a substrate; forming a gate insulation layer on the gate conduction layer; forming a source conduction layer and a drain conduction layer on the gate insulation layer, in which the drain conduction layer has an extension section extending to the pixel electrode region; forming a channel layer on the source conduction layer and the drain conduction layer; and forming a protection layer on the channel layer. The extension section and an electrode layer serve as the upper and lower electrode of the storage capacitor, respectively. Wherein the gate conduction layer, the source conduction layer, the drain conduction layer, and the channel layer are made of metallic oxides.

Abstract: A turbine rotor blade with low cooling flow includes a first forward flowing 5-pass serpentine flow cooling circuit that provides cooling air to a trailing edge row of exit holes and a second forward flowing 3-pass serpentine flow cooling circuit that provides cooling air to a leading edge showerhead arrangement of film cooling holes and to a blade tip cooling channel. The blade tip cooling channel includes a film cooling holes for the blade tip. The low flow cooing circuit provides for cooling of the blade without the need for impingement cooling of the leading edge and trailing edge regions.

Abstract: A light-emitting diode (10) has a light-extracting surface and includes a transparent substrate (14), a compound semiconductor layer (13) bonded to the transparent substrate, a light-emitting part (12) contained in the compound semiconductor layer, a light-emitting layer (133) contained in the light-emitting part and formed of (AlXGa1-X)YIn1-YP(0?X?1, 0<Y?1), first and second electrodes (15, 16) of different polarities provided on a surface of the light-emitting diode opposite the light-extracting surface, and a reflecting metal film (17) formed on the first electrode. The transparent substrate has a first side face (142) virtually perpendicular to a light-emitting surface of the light-emitting layer on a side near the light-emitting layer and a second side face (143) oblique to the light-emitting surface on a side distant from the light-emitting layer. The first and second electrodes are mounted respectively on electrode terminals (43, 44).

Abstract: Films of III-nitride for semiconductor device growth are planarized using an etch-back method. The method includes coating a III-nitride surface having surface roughness features in the micron range with a sacrificial planarization material such as an appropriately chose photoresist. The sacrificial planarization material is then etched together with the III-nitride roughness features using dry etch methods such as inductively coupled plasma reactive ion etching. By closely matching the etch rates of the sacrificial planarization material and the III-nitride material, a planarized III-nitride surface is achieved. The etch-back process together with a high temperature annealing process yields a planarize III-nitride surface with surface roughness features reduced to the nm range. Planarized III-nitride, e.g., GaN, substrates and devices containing them are also provided.