Abstract: A display panel and a display device are provided. The display panel includes a driving circuit and the driving circuit includes N-level shift registers cascaded with each other, where N is greater than or equal to two. A shift register of the N-level shift registers includes: a third control unit, configured to control a signal of a fourth node, the third control unit receives a first voltage signal and a second voltage signal, the first voltage signal is a high-level signal, and the second voltage signal is a low-level signal; and a fourth control unit, configured to generate an output signal, the fourth control unit receives a third voltage signal and a fourth voltage signal. The display panel further includes a pixel circuit, the pixel circuit includes a driving transistor, the driving circuit provides a first driving signal.

Abstract: A display panel and a display device are provided. The display panel includes a driving circuit. The driving circuit includes N-level shift registers cascaded with each other, where N is greater than or equal to two. A shift register of the N-level shift registers includes: a fourth control unit, configured to receive a third voltage signal and a fourth voltage signal, and generate an output signal in response to a signal of a second node and a signal of a fourth node. The display panel further includes a pixel circuit, the pixel circuit includes a driving transistor, a working process of the pixel circuit includes a reset stage and a bias stage, where in the reset stage, the output signal of the driving circuit is a reset signal, and in the bias stage, the output signal of the driving circuit is a bias signal.

Abstract: A display panel and a display device are provided. The display panel includes a driving circuit, and the driving circuit includes N-level shift registers cascaded with each other, where N is greater than or equal to two. A shift register of the N-level shift registers includes: a third control unit, configured to control a signal of a fourth node, the third control unit receives a first voltage signal and a second voltage signal, the first voltage signal is a high-level signal, and the second voltage signal is a low-level signal; and a fourth control unit, configured to generate an output signal, the fourth control unit receives a third voltage signal and a fourth voltage signal, and the third voltage signal is a high-level signal, and the fourth voltage signal is a low-level signal.

Abstract: A display device includes pixels, an image converter generating second image data using first image data of an N-th frame and first image data of an (N+1)th frame; and a data driver supplying a data signal corresponding to the second image data to the pixels during an (N+1)th frame period. The image converter detects a logo and a logo area using the first image data, calculates a first representative value of data corresponding to a peripheral area of the logo area among the first image data of an N-th frame and a second representative value of data corresponding to a reference area among the first image data of the (N+1)th frame, and selectively converts data for the logo among the first image data of the (N+1)th frame according to the first representative value and the second representative value to generate the second image data of the (N+1)th frame.

Abstract: A gate driving circuit includes: a plurality of driving stages, each driving stage configured to provide a gate signal to a corresponding gate line among a plurality of gate lines, wherein each of the plurality of driving stages includes: a first transistor electrically connected between a first clock terminal and a gate output terminal, the first transistor including a gate electrode electrically connected to a first node, the first clock terminal to receive a first clock signal; a second transistor configured to transmit a first carry signal to the first node; and a third transistor electrically connected between the first node and a first voltage terminal, the third transistor including a gate electrode electrically connected to the first voltage terminal, the first voltage terminal to receive a first voltage, wherein the gate output terminal is electrically connected to the corresponding gate line.

Abstract: A display panel and a driving method thereof are provided. The display panel includes a plurality of sub-pixels arranged in an array. The plurality of sub-pixels are divided into a plurality of units arranged along rows and columns, and the unit includes a plurality of the sub-pixels. Polarities of the sub-pixels in any two adjacent sub-units are different, a number of the sub-pixels in any one of the sub-units is less than or equal to 4, and a number of the sub-pixels in one of the sub-units that has a common boundary with the unit is less than or equal to 2.

Abstract: A display driver includes a line latch circuit; a first D/A conversion circuit; a second D/A conversion circuit; a first amplifier circuit configured to initialize charges of a capacitor of a first switched capacitor circuit in a first initialization period and output a data voltage in a first output period; a second amplifier circuit configured to initialize charges of a capacitor of a second switched capacitor circuit in a second initialization period and output a data voltage in a second output period; and a control circuit. The control circuit is configured to end the second initialization period of the second amplifier circuit before display data is latched by the line latch circuit at a latch timing and an output of the first amplifier circuit changes.

Abstract: The present invention discloses a backlight control method having dynamic backlight adjusting mechanism used in a display control circuit is provided and includes the steps outlined below. A frame refresh time length of a former frame is obtained. When a current frame is started to be displayed, a backlight module is controlled to output a strobe backlight in a backlight turn-on time period. When an actual display time reaches the frame refresh time length and a next frame is not started to be displayed, the backlight module is controlled to output a constant backlight until the next frame is started to be displayed. When the actual display time does not reach the frame refresh time length and the next frame is started to be displayed, the backlight module is controlled to output the constant backlight until the frame next to the next frame is started to be displayed.

Abstract: The present disclosure provides a substrate motherboard including: a first substrate base, a first conductive pattern layer, at least one first insulating layer and a second conductive pattern layer which are sequentially arranged. The first conductive pattern layer includes a plurality of signal lines in the active region. The second conductive pattern layer includes a plurality of connection terminals in the active region, and the plurality of connection terminals are electrically coupled to corresponding signal lines in the plurality of signal lines. The substrate motherboard further includes a plurality of leading-out wires and a plurality of detection terminals in the non-active region, first ends of the plurality of leading-out wires are electrically coupled to corresponding connection terminals and extending to the non-active region to be electrically coupled to corresponding detection terminals through second ends thereof.

Abstract: An information processing apparatus includes: a housing; a substrate fixed in the housing; a touch panel installed in the housing and disposed to be inclined in a direction approaching the substrate toward a front of the information processing apparatus; and an opening detection switch provided between an edge of the touch panel on a front side and the substrate. The opening detection switch includes: a contact opening and closing portion fixed to the substrate; a key top having a hemispherical surface in contact with the edge; and an elastic member elastically deformable by a pressing force from the key top pressed by the edge to press down the contact opening and closing portion.

Abstract: The disclosure provides a display panel and a displaying device. The display panel comprises a bonding area and an active area; a flexible printed circuit board, the flexible printed circuit board being arranged on a side, away from the active area, of the bonding area, and comprising a display signal line which extends in a first direction and is electrically connected to the bonding area; and a touch driving line and a signal receiving line, the touch driving line and the signal receiving line being connected to the flexible printed circuit board from the active area via the bonding area, and the display signal line not overlapping with the touch driving line or the signal receiving line.

Abstract: An output circuit includes a first switch that outputs a positive voltage signal received via a first node when in an ON state, a second switch that outputs a negative voltage signal received via a second node when in an ON state, third and fourth switches that set the first and second nodes to a reference power supply voltage when in an ON state, a first follower circuit that generates, as a gate voltage, a voltage signal following and being in phase with a voltage signal of the first node through source follower operation and supplies the gate voltage to a gate of the first switch, and a second follower circuit that generates, as a gate voltage, a voltage signal following and being in phase with a voltage signal of the second node through source follower operation and supplies the gate voltage to a gate of the second switch.

Abstract: An overdrive method includes: performing loss compression to an input image to generate image data, and storing the image data into a memory; reading the image data from the memory and decoding the image data to obtain a previous image; obtaining a current image, calculating a difference between a current grey level at a location of the current image and a previous grey level of the previous image at the location; calculating a gain according to the difference and a threshold; calculating an overdrive grey level according to the current grey level and the previous grey level; and mixing the overdrive grey level and the current grey level based on the gain to generate an output grey level to replace the current grey level.

Abstract: This document describes systems and techniques for image retention mitigation via voltage biasing for organic light-emitting diode (OLED) displays. In aspects, a pixel array is described having pixel circuits including a first transistor configured to receive a biasing signal from one or more drivers and, based on the biasing signal, enable or disable an application of a bias voltage at a terminal of a second transistor. In so doing, the bias voltage reduces a hysteresis effect experienced by the second transistor for each of the multiple pixel circuits of the pixel array, thereby mitigating an image retention.

Abstract: A display device according to an embodiment of the present invention uses, as a threshold value based on which it is determined whether to switch clip processing on or to switch the clip processing off, an activation grayscale level difference threshold value (or an activation grayscale voltage difference threshold value), a deactivation grayscale level difference threshold value (or a deactivation grayscale voltage difference threshold value), an activation pixel number threshold value, and a deactivation pixel number threshold value. The deactivation grayscale level difference threshold value (or the deactivation grayscale voltage difference threshold value) is smaller than the activation grayscale level difference threshold value (or the activation grayscale voltage difference threshold value). The deactivation pixel number threshold value is smaller than the activation pixel number threshold value.

Abstract: A signal transmission device includes a first master signal conversion circuit and at least one first slave signal conversion circuit. The first master signal conversion circuit is configured to receive first partial data of output data from a data generation unit, convert the first partial data of the output data into a first transmission signal correspondingly, and output a first synchronization signal. The at least one first slave signal conversion circuit is configured to receive at least second partial data of the output data and convert the at least second partial data of the output data into at least one second transmission signal correspondingly, wherein the at least one first slave signal conversion circuit controls a timing of the at least one second transmission signal according to the first synchronization signal.

Abstract: A reference voltage generation circuit is provided. The reference voltage generation circuit reduces a potential difference between a reference voltage less than a first data driving voltage and a data driving voltage, namely, the potential difference between a lower reference voltage and the data driving voltage is reduced. Therefore, the power loss of a voltage dividing module is reduced to prevent the problems of reduced reliability and reduced service life of a drive circuit board due to excessive internal temperature.

Abstract: The present invention provides a dimming panel including: a drive circuit; and dimming units arranged in one direction from a drive circuit, the dimming panel sequentially including a first substrate, a liquid crystal layer, and a second substrate, the first substrate sequentially including an insulating substrate, connection lines formed from a transparent conductive material and connected to the drive circuit, a first insulating layer, a first electrode, a second insulating layer, and a second electrode, the first electrode or the second electrode including dimming electrodes disposed for the respective dimming units, each of the dimming electrodes being electrically connected to one of the connection lines, an electrode width of at least one of the connection lines increasing in response to a distance from the drive circuit.

Abstract: An organic light-emitting diode (OLED) display is disclosed.

Abstract: A source driver includes a latch unit sequentially retrieving a video data signal for each data row corresponding to each of a first to n th horizontal scanning lines of the display panel, an overdrive arithmetic circuit calculating an overdrive value of the drive voltage applied to the pixel portions on an N th line based on a comparison result of comparing the data row corresponding to the N th line among the first to n th horizontal scanning lines and the data row corresponding to an (N?1) th line and a distance to the N th line from the source driver, and a voltage output unit generating the drive voltage applied to the pixel portions on the N th line based on the data row corresponding to the N th line and the overdrive value to output to the source line.