Abstract: Disclosed herein is a semiconductor device with high reliability which has TFT of adequate structure arranged according to the circuit performance required. The semiconductor has the driving circuit and the pixel portion on the same substrate. It is characterized in that the storage capacitance is formed between the first electrode formed on the same layer as the light blocking film and the second electrode formed from a semiconductor film of the same composition as the drain region, and the first base insulating film is removed at the part of the storage capacitance so that the second base insulating film is used as the dielectric of the storage capacitance. This structure provides a large storage capacitance in a small area.

Abstract: A method of filling vias for a PCRAM cell with a metal is described. A PCRAM intermediate structure including a substrate, a first conductor, and an insulator through which a via extends has a metallic material formed within the via and on a surface of the insulator. The metallic material may be deposited on the surface and within the via. A hard mask of a flowable oxide is deposited over the metallic material in the via to protect the metallic material in the via. A subsequent dry sputter etch removes the metallic material from the surface of the insulator and a portion of the hard mask. After complete removal of the hard mask, a glass material is recessed over the metallic material in the via. Then, a layer of a metal-containing material is formed over the glass material. Finally, a second conductor is formed on the surface of the insulator.

Abstract: A vertical transistor forming method includes forming a first pillar above a first source/drain and between second and third pillars, providing a first recess between the first and second pillars and a wider second recess between the first and third pillars, forming a gate insulator over the first pillar, forming a front gate and back gate over opposing sidewalls of the first pillar by depositing a gate conductor material within the first and second recesses and etching the gate conductor material to substantially fill the first recess, forming the back gate, and only partially fill the second recess, forming the front gate, forming a second source/drain elevationally above the first source/drain, and providing a transistor channel in the first pillar. The channel is operationally associated with the first and second sources/drains and with the front and back gates to form a vertical transistor configured to exhibit a floating body effect.

Abstract: A method for fabricating substrate material to include trenches and unreleased beams with submicron dimensions includes etching a first oxide layer on the substrate to define a first set of voids in the first oxide layer to expose the substrate. A second oxide layer is accreted to the first oxide layer to narrow the first set of voids to become a second set of voids on the substrate. A polysilicon layer is deposited over the second oxide layer, the first oxide layer and the substrate. A third set of voids is etched into the polysilicon layer. Further etching widens the third set of voids to define a fourth set of voids to expose the first oxide layer and the substrate. The first oxide layer and the substrate is deeply etched to define beams and trenches in the substrate.

Abstract: A method for producing a semiconductor structure that includes at least one useful layer on a substrate.

Abstract: A semiconductor manufacturing method comprises forming a leveling guard ring defining an interior area into which are fabricated one or more devices. In certain embodiments two or more matched devices, such as in a common centroid layout, are fabricated in the interior area. The guard ring is formed on at least one particular layer for a particular processing step. By the guard ring overwhelming the effect of local features' elevation differences, photoresist thereafter applied consequently has a more uniform height across the interior area, resulting in more uniform devices. In some embodiments, a plurality of guard rings enclosing respective arrays of matched devices are arranged over the surface of a semiconductor wafer, spaced apart so as to be not local to one another. Based on the equalizing effect by each of the guard rings, the respective devices arranged in the interior areas are more evenly matched to equivalent devices in far-spaced guard rings. Thus, both local and global matching are achieved.

Abstract: A method of processing a substrate of a device comprises the as following steps. Form a cap layer over the substrate. Form a dummy layer over the cap layer, the cap layer having a top surface. Etch the dummy layer forming patterned dummy elements of variable widths and exposing sidewalls of the dummy elements and portions of the top surface of the cap layer aside from the dummy elements. Deposit a spacer layer over the device covering the patterned dummy elements and exposed surfaces of the cap layer. Etch back the spacer layer forming sidewall spacers aside from the sidewalls of the patterned dummy elements spaced above a minimum spacing and forming super-wide spacers between sidewalls of the patterned dummy elements spaced less than the minimum spacing. Strip the patterned dummy elements. Expose portions of the substrate aside from the sidewall spacers. Pattern exposed portions of the substrate by etching into the substrate.

Abstract: This disclosure describes system(s) and/or method(s) enabling contacts for individual nanometer-scale-thickness layers of a multilayer film.

Abstract: A low-k interconnect dielectric layer is strengthened by forming pillars of hardened material in the low-k film. An E-beam source is used to expose a plurality of pillar locations. The locations are exposed with a predetermined power and exposure time to convert the low-k film in the selected locations to pillars having higher hardness and strength than the surrounding portions of the low-k film.

Abstract: The invention is directed to a hermetically sealed device and a method for making such device. The device includes optical, micro-electromechanical, electronic and opto-electronic devices, having a substrate with one or a plurality of optical, opto-electronic, electronic or micro-electromechanical (“MEMS”) elements either singly or in combination that are located on a substrate; a covering having a top part and an extension extending a distance from the top part from the top part, an adhesive that is used to bond the extension portion of the covering to the substrate; and a sealing agent for hermetically sealing the area where the covering extension is bonded to the substrate. In the method of the invention the sealing agent is applied using atomic layer deposition techniques.

Abstract: A semiconductor device is fabricated by forming a trench in a semiconductor body. A region of dielectric material is formed within at least a lower portion of the trench. An upper portion of the semiconductor body is doped. A cutout is formed in the semiconductor material such that a vertical strip of semiconductor material remains along a sidewall of the dielectric material. A lower portion of the semiconductor body adjacent the sidewall of the dielectric material is doped. A gate dielectric layer is formed over the vertical strip of semiconductor material and a gate electrode is arranged in the cutout.

Abstract: The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric material and an upper region comprising atoms of Si, C and H located above the hermetic oxide material. The present invention also provides a method of fabricating the inventive hardmask as well as a method to form an interconnect structure containing the same.

Abstract: A capacitor device selectively combines MOM, MIM and varactor regions in the same layout area of an IC. Two or more types of capacitor regions arranged vertically on a substrate to form the capacitor device. This increase the capacitance per unit of the capacitor device, without occupying an extra layout area.

Abstract: A memory cell which is formed on a substrate of a first conductivity type. A pillar of the first conductivity type extends vertically upward from the substrate. A source region of a second conductivity type is formed in the substrate extending adjacent to and away from a base of the pillar. A drain region of the second conductivity type is formed in an upper region of the pillar. A gate dielectric and conductor are arranged along a first side of the pillar. A capacitor dielectric and body capacitor plate are arranged along an opposite, second side of the pillar. A depletion region around the source region defines a floating body region within the pillar which forms both a body of an access transistor structure and a plate of a capacitor structure. The cell also provides gain with respect to charge stored within the floating body.

Abstract: An electrode structure includes a first layer of conductive material and a dielectric layer formed on a surface of the first layer. An opening is formed in the dielectric layer to expose a portion of the surface of the first layer. A binding layer is formed on the dielectric layer and on the exposed portion of the surface of the first layer and a second layer of conductive material is formed on the conductive binding layer. The binding layer can be an oxide and the second layer a conductive material that is diffusible into an oxide. The electrode structure can be annealed to cause conductive material from the second layer to be chemisorbed into the binding layer to improve adhesion between the first and second layers. A programmable cell can be formed by forming a doped glass layer in the electrode structure.

Abstract: A chip-type solid electrolytic capacitor comprises capacitor elements. A cathode terminal comprising a plate-like conductor is interposed between cathode layers of the capacitor elements. The capacitor elements are bonded to each other by a bonding agent such as a solder or a conductive adhesive. The cathode terminal is provided with a through hole formed at a portion to be brought into contact with each of the capacitor elements. Bonding surfaces of the capacitor elements are directly connected at the through hole.

Abstract: A nickel silicon alloy barrier layer formed between a metal bonding pad on an integrated circuit and a tin-based solder ball, for example, a lead-free solder. The nickel silicon alloy contains at least 2 wt % silicon and preferably less than 20 wt %. An adhesion layer may be formed between the barrier layer and the bonding pad. For copper metallization, the adhesion layer may contain titanium or tantalum; for aluminum metallization, it may be aluminum. The nickel silicon alloy may be deposited by magnetron sputtering. Commercially available NiSi4.5% sputter targets have provided a superior under-bump metallization (UBM) with lead-free tin solder bumps. Dopants other than silicon/may be used to reduce the magnetic permeability and provide other advantages of the invention.

Abstract: The object of the disclosure is to measure temperature using pyrometers, in a simple and economic way, enabling precise temperature measurement, even for low temperatures. The disclosure presents an apparatus and method for thermally treating substrates, wherein the substrate is exposed to at least a first and at least a second radiation; the predetermined wavelengths of the first radiation are absorbed between the first radiation source and the substrate; a radiation from the substrate is measured in the predetermined wavelength using a radiation detector arranged on the same side as a second radiation source; the second radiation from the second radiation source is modulated and determined.

Abstract: A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode is formed on the gate electrode insulating film, and an oxidation process using ozone is performed to sufficiently round the shape of the lower edge of the gate electrode.

Abstract: An ideal step-profile in a channel region is realized easily and reliably, whereby suppression of the short-channel effect and prevention of mobility degradation are achieved together. A silicon substrate is amorphized to a predetermined depth from a semiconductor film, and impurities to become the source/drain are introduced in this state. Then the impurities are activated, and the amorphized portion is recrystallized, by low temperature solid-phase epitaxial regrowth. With the processing temperature required for the low temperature solid-phase epitaxial regrowth being within a range of 450° C.-650° C., thermal diffusion of the impurities into the semiconductor film is suppressed, thereby maintaining the initial steep step-profile.