Patents Examined by Vernon P Webb
  • Patent number: 8406429
    Abstract: An apparatus for spatially separating sounds from at least two sound sources includes a sound detection unit and a sound control unit. The sound detection unit detects a first sound from a first sound source while a second sound is outputted from a second sound source. The sound control unit performs a head-related transfer function (HRTF) on the second sound to move the second sound to a user's desired position according to the detection result, thereby the second sound is set as a background sound.
    Type: Grant
    Filed: October 16, 2008
    Date of Patent: March 26, 2013
    Assignee: Expamedia, Inc.
    Inventors: Dae-Woo Kim, Ho-Jun Park, Hyun-Moo Jung
  • Patent number: 8383449
    Abstract: A thin film transistor array panel includes a substrate, a plurality of first and second signal lines crossing each other on the substrate, source electrodes connected to the first signal lines, drain electrodes connected to the second signal lines, pixel electrodes connected to the drain electrodes, a first partition formed on the source and drain electrodes and having a first opening, wherein a lower width of the first opening is wider than an upper width of the first opening, an organic semiconductor formed in the first opening and at least overlapping the portions of the source electrode and the drain electrode, and a gate electrode connected to the second signal line and at least overlapping the portion of the organic semiconductor.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: February 26, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Keun-Kyu Song, Tae-Young Choi, Tae-Hyung Hwang, Seung-Hwan Cho
  • Patent number: 8372730
    Abstract: An electric fuse includes: a first interconnect and a second interconnect, formed on a semiconductor substrate; a fuse link, formed on the semiconductor substrate and provided so that an end thereof is coupled to the first interconnect, the fuse link being capable of electrically cutting the second interconnect from the first interconnect; and an electric current inflow terminal and an electric current drain terminal for cutting the fuse link, formed on the semiconductor substrate and provided in one end and another end of the first interconnect, respectively.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: February 12, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Takehiro Ueda
  • Patent number: 8372693
    Abstract: In a stacked-type semiconductor device, a first semiconductor device and at least one second semiconductor device are stacked. The first semiconductor device includes a wiring board and a first semiconductor chip mounted on the wiring board. The second semiconductor device includes a wiring board and a second semiconductor chip mounted on the wiring board. The thickness of the second semiconductor chip of each second semiconductor device is thicker than the thickness of the first semiconductor chip.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: February 12, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Mitsuaki Katagiri, Hisashi Tanie, Jun Kayamori, Dai Sasaki, Hiroshi Moriya
  • Patent number: 8368165
    Abstract: A SiC Schottky diode which includes a Schottky barrier formed on a silicon face 4H—SiC body.
    Type: Grant
    Filed: October 16, 2006
    Date of Patent: February 5, 2013
    Assignee: Siliconix Technology C. V.
    Inventor: Giovanni Richieri
  • Patent number: 8362455
    Abstract: Provided are a resistive random access memory device and a method of manufacturing the same. The resistive random access memory device includes a switching device and a storage node connected to the switching device, and the storage node includes a first electrode and a second electrode and a resistance change layer formed of Cu2-XO between the first electrode and the second electrode.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: January 29, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-jun Choi, Jung-hyun Lee, Hyung-jin Bae, Chang-soo Lee
  • Patent number: 8363847
    Abstract: An aliasing correction in a wave field synthesis system is achieved by ascertaining the aliasing filter property specific for a virtual source. This aliasing filter property, which, for example, may be the aliasing frequency is ascertained by help of the source position information. This aliasing filter property is used for an adaptive anti-aliasing filter for adaptive filtering of the audio signal associated with the source or the component signals associated with the source.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: January 29, 2013
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der Angewandten Forschung e.V.
    Inventors: Joachim Deguara, René Rodigast
  • Patent number: 8357942
    Abstract: In a semiconductor device by which peripheral circuit sections, such as a semiconductor element, a matching circuit section, a bias circuit section, a capacitor element, are placed on and connected to a substrate, the semiconductor element can be grounded, and the semiconductor device which can make heat radiation characteristics of the semiconductor element satisfactory is provided, without providing a via hole into a semiconductor substrate. It includes: a semiconductor element (2) placed on a substrate (1); peripheral circuit sections (30) and (40) placed on the substrate (1) and connected with the semiconductor element (2); an electrode (30e) provided in the peripheral circuit section (30) and grounded; an electrode (30s) for grounding connected to a metal layer (30m), a metal layer (30m) and a source electrode (2s) of the semiconductor element (2); and an electrode (30d) connected to a gate electrode (2g) of the semiconductor element (2).
    Type: Grant
    Filed: October 1, 2007
    Date of Patent: January 22, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Takagi
  • Patent number: 8344478
    Abstract: Inductors and methods for integrated circuits that result in inductors of a size compatible with integrated circuits, allowing the fabrication of inductors, with or without additional circuitry on a first wafer and the bonding of that wafer to a second wafer without wasting of wafer area. The inductors in the first wafer are comprised of coils formed by conductors at each surface of the first wafer coupled to conductors in holes passing through the first wafer. Various embodiments are disclosed.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: January 1, 2013
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Joseph P. Ellul, Khanh Tran, Edward Martin Godshalk, Albert Bergemont
  • Patent number: 8319281
    Abstract: A semiconductor device capable of inhibiting a fabricating process from complication while inhibiting the dielectric strength voltage of a insulating film from reduction is obtained. This semiconductor device includes a groove portion, an insulating film formed on a surface of the groove portion, a gate electrode and a source impurity region, wherein upper ends of the gate electrode, which are portions in contact with the insulating film, are each located at a position identical with or deeper than the range of an impurity introduced from a surface of a semiconductor substrate with respect to the insulating film in order to form the source impurity region and above a lower surface of the source impurity region.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: November 27, 2012
    Assignee: Sanyo Electric, Co., Ltd.
    Inventors: Yoshikazu Yamaoka, Satoru Shimada, Kazunori Fujita, Kazuhiro Sasada
  • Patent number: 8304280
    Abstract: A thin film transistor array panel includes a substrate, a plurality of first and second signal lines crossing each other on the substrate, source electrodes connected to the first signal lines, drain electrodes connected to the second signal lines, pixel electrodes connected to the drain electrodes, a first partition formed on the source and drain electrodes and having a first opening, wherein a lower width of the first opening is wider than an upper width of the first opening, an organic semiconductor formed in the first opening and at least overlapping the portions of the source electrode and the drain electrode, and a gate electrode connected to the second signal line and at least overlapping the portion of the organic semiconductor.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: November 6, 2012
    Assignee: Samsung Display Co., Ltd.
    Inventors: Keun-Kyu Song, Tae-Young Choi, Tae-Hyung Hwang, Seung-Hwan Cho
  • Patent number: 8304767
    Abstract: Provided is a crystalline silicon thin film semiconductor device which is capable of reducing off-state leakage current and has excellent current rising characteristics. The thin film transistor includes a semiconductor layer formed of an amorphous silicon layer and a crystalline silicon layer. A drain electrode is provided in direct contact with the crystalline silicon layer of the semiconductor layer, to thereby improve the current rising characteristics.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: November 6, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventor: Masahiro Tamura
  • Patent number: 8300858
    Abstract: An electrostatic speaker is constituted of a vibrator, conductive cloths, and elastic members, which are laminated together and woven together using strings. Since all the constituent elements are restrained in positioning by strings, the overall structure thereof is not substantially changed even when the electrostatic speaker is deformed in shape by bending or curving, wherein it is possible to secure the prescribed positional relationship between the constituent elements, which are not deviated in positioning. It is possible to introduce a sheet composed of a thermoplastic resin, which holds the vibrator and elastic members therein. The conductive cloths can be replaced with film electrodes, each of which is formed such that a conductive polymer layer is formed on a base film composed of a thermoplastic resin.
    Type: Grant
    Filed: September 15, 2008
    Date of Patent: October 30, 2012
    Assignee: Yamaha Corporation
    Inventors: Takao Nakaya, Yasuaki Takano
  • Patent number: 8288802
    Abstract: A spacer structure contains a carbon-containing oxynitride film positioned on a gate sidewall and a nitride film covering the carbon-containing oxide film. The carbon-containing oxynitride film has low etch rate so that the spacer structure can have a good profile during etching the carbon-containing oxynitride film.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: October 16, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Po-Lun Cheng, Che-Hung Liu
  • Patent number: 8269211
    Abstract: An organic electronic device including: a first layer including a conductive or semiconductive organic material; a second layer including a conductive or semiconductive inorganic material, and in contact with the first layer; and an interface layer between the first layer and the second layer, wherein the interface layer includes a conductive or semiconductive organic material and a conductive or semiconductive inorganic material.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: September 18, 2012
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sin-Doo Lee, Jin-Hyuk Bae
  • Patent number: 8264084
    Abstract: A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes: a) Lithographically patterning the top metal layer into the contact zones and the contact enhancement zones. b) Forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: September 11, 2012
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: François Hébert, Anup Bhalla, Kai Liu, Ming Sun
  • Patent number: 8241978
    Abstract: A semiconductor device having integrated MOSFET and Schottky diode includes a substrate having a MOSFET region and a Schottky diode region defined thereon; a plurality of first trenches formed in the MOSFET region; and a plurality of second trenches formed in the Schottky diode region. The first trenches respectively including a first insulating layer formed over the sidewalls and bottom of the first trench and a first conductive layer filling the first trench serve as a trenched gate of the trench MOSFET. The second trenches respectively include a second insulating layer formed over the sidewalls and bottom of the second trench and a second conductive layer filling the second trench. A depth and a width of the second trenches are larger than that of the first trenches; and a thickness of the second insulating layer is larger than that of the first insulating layer.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: August 14, 2012
    Assignee: Anpec Electronics Corporation
    Inventors: Wei-Chieh Lin, Li-Cheng Lin, Hsin-Yu Hsu, Ho-Tai Chen, Jen-Hao Yeh, Guo-Liang Yang, Chia-Hui Chen, Shih-Chieh Hung
  • Patent number: 8242488
    Abstract: Disclosed is an organic electroluminescent device having high external quantum efficiency and long emission life and an illuminating device and a display device, each comprising the organic electroluminescent device. The organic electroluminescent device comprises at least an anode and a cathode arranged on a supporting substrate and at least two organic layers, namely a first layer and a second layer, between the anode and the cathode, in which the organic electroluminescent device is characterized in that the first organic layer contains a light emitting dopant and the second organic layer contains a charge-transporting material and a part of the material constituting the first organic layer, and the second organic layer is formed by coating after formation of the first organic layer.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: August 14, 2012
    Assignee: Konica Minolta Holdings, Inc.
    Inventors: Rie Katakura, Hiroshi Kita, Hideo Taka
  • Patent number: 8242573
    Abstract: There are provided a semiconductor device and a method of forming the same. The semiconductor device may include a semiconductor substrate including a digital circuit region and an analog circuit region, a device isolation layer on the boundary between the digital circuit region and the analog circuit region, a conductive region adjacent to the side surface and the bottom surface of the isolation layer, and a ground pad which is electrically connected to the conductive region and to which a ground voltage is applied.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: August 14, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-Su Kim, Jin-Sung Lim
  • Patent number: 8237251
    Abstract: In a stacked-type semiconductor device, a first semiconductor device and at least one second semiconductor device are stacked. The first semiconductor device includes a wiring board and a first semiconductor chip mounted on the wiring board. The second semiconductor device includes a wiring board and a second semiconductor chip mounted on the wiring board. The thickness of the second semiconductor chip of each second semiconductor device is thicker than the thickness of the first semiconductor chip.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: August 7, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Mitsuaki Katagiri, Hisashi Tanie, Jun Kayamori, Dai Sasaki, Hiroshi Moriya