Abstract: An erase method where a corner portion on which an electric field concentrates locally is provided on the memory gate electrode, and charges in the memory gate electrode are injected into a charge trap film in a gate dielectric with Fowler-Nordheim tunneling operation is used. Since current consumption at the time of erase can be reduced by the Fowler-Nordheim tunneling, a power supply circuit area of a memory module can be reduced. Since write disturb resistance can be improved, a memory array area can be reduced by adopting a simpler memory array configuration. Owing to both the effects, an area of the memory module can be largely reduced, so that manufacturing cost can be reduced. Further, since charge injection centers of write and erase coincide with each other, so that (program and erase) endurance is improved.

Abstract: The present invention improves the efficiency of conversion from a non-radiation two-dimensional electron plasmon wave into a radiation electromagnetic wave, and realizes a wide-band characteristic. A terahertz electromagnetic wave radiation element of the present invention comprises a semiinsulating semiconductor bulk layer, a two-dimensional electron layer formed directly above the semiconductor bulk layer by a semiconductor heterojunction structure, source and drain electrodes electrically connected to two opposed sides of the two-dimensional electron layer, a double gate electrode grating which is provided in the vicinity of and parallel to the upper surface of the two-dimensional electron layer and for which two different dc bias potentials can be alternately set, and a transparent metal mirror provided in contact with the lower surface of the semiconductor bulk layer, formed into a film shape, functioning as a reflecting mirror in the terahertz band, and being transparent in the light wave band.

Abstract: The present invention provides a lighting device package with one or more light-emitting elements operatively coupled to a substrate and a frame disposed at least in part around the one or more light-emitting elements. The frame and substrate define a cavity in which the one or more light-emitting elements are positioned, wherein this cavity can be substantially enclosed by an optically transmissive system. At least a portion of the cavity can be filled with an encapsulation material. The frame defines one or more passageways, wherein each passageway interconnects the cavity with the outside through an outside port. For example, the outside port can be accessible from the ambient when the lighting device package is in an assembled state, thereby enabling fluidic movement of the encapsulation material into and/or out of the cavity.

Abstract: A semiconductor device includes an NMOS transistor and a PMOS transistor. The NMOS transistor includes a channel area formed in a silicon substrate, a gate electrode formed on a gate insulating film in correspondence with the channel area, and a source area and a drain area formed in the silicon substrate having the channel area situated therebetween. The PMOS transistor includes another channel area formed in the silicon substrate, another gate electrode formed on another gate insulating film in correspondence with the other channel area, and another source area and another drain area formed in the silicon substrate having the other channel area situated therebetween. The gate electrode has first sidewall insulating films. The other gate electrode has second sidewall insulating films. The distance between the second sidewall insulating films and the silicon substrate is greater than the distance between the first sidewall insulating films and the silicon substrate.

Abstract: A nitride semiconductor light-emitting device comprises a substrate, and a first n-type nitride semiconductor layer, an emission layer, a p-type nitride semiconductor layer, a metal layer and a second n-type nitride semiconductor layer stacked on the substrate successively from the side closer to the substrate, with an electrode provided on the surface of the second n-type nitride semiconductor layer or above the surface of the second n-type nitride semiconductor layer. The metal layer is preferably made of a hydrogen-storage alloy.

Abstract: A nitride-based semiconductor light emitting device having an improved structure in which light extraction efficiency is improved and a method of manufacturing the same are provided. The nitride-based semiconductor light emitting device comprises an n-clad layer, an active layer, and a p-clad layer, which are sequentially stacked on a substrate, wherein the n-clad layer comprises a first clad layer, a second clad layer, and a light extraction layer interposed between the first clad layer and the second clad layer and composed of an array of a plurality of nano-posts, the light extraction layer diffracting or/and scattering light generated in the active layer.

Abstract: A method of fabricating a single crystal gallium nitride substrate the step of cutting an ingot of single crystal gallium nitride along predetermined planes to make one or more single crystal gallium nitride substrates. The ingot of single crystal gallium nitride is grown by vapor phase epitaxy in a direction of a predetermined axis. Each predetermined plane is inclined to the predetermined axis. Each substrate has a mirror polished primary surface. The primary surface has a first area and a second area. The first area is between an edge of the substrate and a line 3 millimeter away from the edge. The first area surrounds the second area. An axis perpendicular to the primary surface forms an off-angle with c-axis of the substrate. The off-angle takes a minimum value at a first position in the first area of the primary surface.

Abstract: In order to form a plurality of semiconductor elements over an insulating surface, in one continuous semiconductor layer, an element region serving as a semiconductor element and an element isolation region having a function to electrically isolate element regions from each other by repetition of PN junctions. The element isolation region is formed by selective addition of an impurity element of at least one or more kinds of oxygen, nitrogen, and carbon and an impurity element that imparts an opposite conductivity type to that of the adjacent element region in order to electrically isolate elements from each other in one continuous semiconductor layer.

Abstract: A circuit board for a light emitting diode package improved in heat radiation efficiency and a manufacturing method thereof. In a simple manufacturing process, insulating layers are formed by anodizing on a portion of a thermally conductive board body and plated with a conductive material. In the light emitting diode package, a board body is made of a thermally conductive metal. Insulating oxidation layers are formed at a pair of opposing edges of the board body. First conductive patterns are formed on the insulating oxidation layers, respectively. Also, second conductive patterns are formed in contact with the board body at a predetermined distance from the first conductive patterns, respectively. The light emitting diode package ensures heat generated from the light emitting diode to radiate faster and more effectively. Additionally, the insulating layers are formed integral with the board body by anodizing, thus enhancing productivity and durance.

Abstract: A method of fabricating short-gate-length electrodes for integrated III-V compound semiconductor devices, particularly for integrated HBT/HEMT devices on a common substrate is disclosed. The method is based on dual-resist processes, wherein a first thin photo-resist layer is utilized for defining the gate dimension, while a second thicker photo-resist layer is used to obtain a better coverage on the surface for facilitating gate metal lift-off. The dual-resist method not only reduces the final gate length, but also mitigates the gate recess undercuts, as compared with those fabricated by the conventional single-resist processes. Furthermore, the dual-resist method of the present invention is also beneficial for the fabrication of multi-gate device with good gate-length uniformity.

Abstract: A photodetector array includes a semiconductor substrate having opposing first and second main surfaces, a first layer of a first doping concentration proximate the first main surface, and a second layer of a second doping concentration proximate the second main surface. The photodetector includes at least one conductive via formed in the first main surface and an anode/cathode region proximate the first main surface and the at least one conductive via. The via extends to the second main surface. The conductive via is isolated from the semiconductor substrate by a first dielectric material. The anode/cathode region is a second conductivity opposite to the first conductivity. The photodetector includes a doped isolation region of a third doping concentration formed in the first main surface and extending through the first layer of the semiconductor substrate to at least the second layer of the semiconductor substrate.

Abstract: An electro-optic device substrate includes a base and a TFT element having a source region and a drain region disposed on the base. The TFT element includes a silicon layer in the source region or the drain region, and the silicon layer at least partially includes a silicided portion. The electro-optic device substrate also includes a metal wire connected to the silicided portion of the silicon layer.

Abstract: A memory device includes, a first electrode element, generally planar in form, having an inner contact surface. Then there is a cylindrical cap layer, spaced from the first electrode element, and a phase change element having contact surfaces in contact with the first electrode contact surface and the cap layer, in which the lateral dimension of the phase change element is less than that of the first electrode element and the cylindrical cap layer. A second electrode element extends through the cap layer to make contact with the phase change element. Side walls aligned with the cap layer, composed of dielectric fill material, extend between the first electrode elements and the cap layer, such that the phase change element, the contact surface of the first electrode element and the side walls define a gas-filled thermal isolation cell adjacent the phase change element.

Abstract: An electronic device can include an interconnect level (16) including a bonding pad region (110). An insulating layer (18) can overlie the interconnect level (16) and include an opening (112, 24) over the bonding pad region (110). In one embodiment, a conductive stud (34) can lie within the opening (112, 24) and can be substantially encapsulated. In another embodiment, the electronic device can include a barrier layer (22) lying along a side and a bottom of the opening (112, 24) and a conductive stud (34) lying within the opening (112, 24). The conductive stud (34) can substantially fill the opening (112, 24). A majority of the conductive stud (34) can lie within the opening (112, 24). In still another embodiment, a process for forming an electronic device can include forming a conductive stud (34) within the opening (112, 24) wherein the conductive stud (34) lies substantially completely within the opening (112, 24).

Abstract: A semiconductor IC-embedded module 100 comprises a multilayer substrate 101 having first and second insulating layers 101a and 101b, and a controller IC 012 and memory IC 103 that are embedded in the multilayer substrate 101. A wiring layer 104 is formed as an internal layer in the multilayer substrate 101. Part of the wiring layer 104 constitutes a bus line 104X. The controller IC 102 or memory IC 103 is embedded in the second insulating layer 101b. First and second ground layers 105a and 105b are provided respectively in the first and second insulating layers 101a and 101b. The effect of noise generated by bus lines is reduced, and an additional reduction in noise and a decrease in size and thickness are achieved by laying out bus lines that connect the semiconductor ICs so that distances are minimized.

Abstract: A thin film transistor array panel includes a substrate, a plurality of first and second signal lines crossing each other on the substrate, source electrodes connected to the first signal lines, drain electrodes connected to the second signal lines, pixel electrodes connected to the drain electrodes, a first partition formed on the source and drain electrodes and having a first opening, wherein a lower width of the first opening is wider than an upper width of the first opening, an organic semiconductor formed in the first opening and at least overlapping the portions of the source electrode and the drain electrode, and a gate electrode connected to the second signal line and at least overlapping the portion of the organic semiconductor.

Abstract: A semiconductor device includes a pair of selective gate lines formed above a semiconductor substrate, plural word lines formed above the substrate, plural contact plugs located between the selective gate lines, a first insulator formed in the trenches between the word lines, the first insulator including a first insulating film having a first upper surface flush with the substrate surface, a second insulator formed in the trenches between the contact plugs and including second and third insulating films, and a boro-phosphor-silicate glass film formed on the third insulating film and between the contact plugs. The second insulating film is of a kind same as the first insulating film. The third insulating film has a higher resistance to a wet etching process than the second insulating film. An interface between the second and third insulating films is located between a bottom and an upper end of the trench.

Abstract: A vertical GaN-based LED includes an n-type bonding pad; an n-electrode formed under the n-type bonding pad; a light-emitting structure formed by sequentially laminating an n-type GaN layer, an active layer, and a p-type GaN layer under the n-electrode; a p-electrode formed under the light-emitting structure; and a support layer formed under the p-electrode. The light-emitting structure has or or more trenches which are spaced at a predetermined distance with the n-electrode from the outermost side of the light-emitting structure and in which the active layer of the light-emitting structure is removed.

Abstract: A pn-junction compound semiconductor light-emitting device is provided, which comprises a stacked structure including a light-emitting layer composed of an n-type or a p-type aluminum gallium indium phosphide and a light-permeable substrate for supporting the stacked structure, and the stacked structure and the light-permeable substrate being joined together, wherein the stacked structure includes an n-type or a p-type conductor layer, the conductor layer and the substrate are joined together, and the conductor layer is composed of a Group III-V compound semiconductor containing boron.

Abstract: A light emitting device package including a transparent cover having an electrode pattern formed on a bottom surface thereof; a light emitting device installed below the transparent cover and electrically connected to an external circuit via the electrode pattern; a fixing resin which fixes the light emitting device onto the bottom surface of the transparent cover; and a metal slug provided under the fixing resin to dissipate heat away from the light emitting device.