Patents Examined by Vernon P Webb
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Patent number: 9955268Abstract: A micro-electrical-mechanical system (MEMS) microphone includes a MEMS structure, having a substrate, a diaphragm, and a backplate, wherein the substrate has a cavity and the backplate is between the cavity and the diaphragm. The backplate has multiple venting holes, which are connected to the cavity and allows the cavity to extend to the diaphragm. Further, an adhesive layer is disposed on the substrate, surrounding the cavity. A cover plate is adhered on the adhesive layer, wherein the cover plate has an acoustic hole, dislocated from the cavity without direct connection.Type: GrantFiled: July 11, 2014Date of Patent: April 24, 2018Assignee: Solid State System Co., Ltd.Inventors: Tsung-Min Hsieh, Chien-Hsing Lee, Cheng-Wei Tsai, Jhyy-Cheng Liou
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Patent number: 9941366Abstract: Described herein is a semiconductor device comprising: a semiconductor substrate; a trench provided at a surface of the semiconductor substrate; a first insulating layer covering an inner surface of the trench; and a second insulating layer located at a surface of the first insulating layer in the trench. A refraction index of the first insulating layer is larger than a refraction index of the second insulating layer.Type: GrantFiled: October 14, 2014Date of Patent: April 10, 2018Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Atsushi Onogi, Shinichiro Miyahara
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Patent number: 9924283Abstract: This application relates to a systems and methods for enhanced dynamics processing of streaming audio by source separation and remixing for hearing assistance devices, according to one example. In one embodiment, an external streaming audio device processes sources isolated from an audio signal using source separation, and mixes the resulting signals back into the unprocessed audio signal to enhance individual sources while minimizing audible artifacts. Variations of the present system use source separation in a side chain to guide processing of a composite audio signal.Type: GrantFiled: October 31, 2016Date of Patent: March 20, 2018Assignee: Starkey Laboratories, Inc.Inventor: Kelly Fitz
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Patent number: 9911817Abstract: Field-plate structures are disclosed for electrical field management in semiconductor devices. A field-plate semiconductor structure includes a semiconductor substrate, a source ohmic contact, a drain ohmic contact, and a gate contact disposed over a gate region between the source ohmic contact and the drain ohmic contact, and a source field plate connected to the source ohmic contact. A field-plate dielectric is disposed over the semiconductor substrate. An encapsulating dielectric is disposed over the gate contact, wherein the encapsulating dielectric covers a top surface of the gate contact. The source field plate is disposed over the field-plate dielectric in a field plate region, from which the encapsulating dielectric is absent.Type: GrantFiled: July 18, 2016Date of Patent: March 6, 2018Assignee: Cambridge Electronics, Inc.Inventors: Ling Xia, Mohamed Azize, Bin Lu
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Patent number: 9905464Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a first and second fin shaped structures, a first and second gate structures and a first and second plugs. The first and second fin shaped structures are disposed on a first region and a second region of a substrate and the first and second gate structure are disposed across the first and second fin shaped structures, respectively. A dielectric layer is disposed on the substrate, covering the first and second gate structure. The first and second plugs are disposed in the dielectric layer, wherein the first plug is electrically connected first source/drain regions adjacent to the first gate structure and contacts sidewalls of the first gate structure, and the second plug is electrically connected to second source/drain regions adjacent to the second gate structure and not contacting sidewalls of the second gate structure.Type: GrantFiled: February 3, 2016Date of Patent: February 27, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Hsiang Hung, Ssu-I Fu, Chao-Hung Lin, Chih-Kai Hsu, Jyh-Shyang Jenq
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Patent number: 9905559Abstract: A semiconductor device includes a first fin structure disposed on a substrate. The first fin structure extends in a first direction. A first sacrificial layer pattern is disposed on the first fin structure. The first sacrificial layer pattern includes a left portion and a right portion arranged in the first direction. A dielectric layer pattern is disposed on the first fin structure and interposed between the left and right portions of the first sacrificial layer pattern. A first active layer pattern extending in the first direction is disposed on the first sacrificial layer pattern and the dielectric layer pattern. A first gate electrode structure is disposed on a portion of the first active layer pattern. The portion of the first active layer is disposed on the dielectric layer pattern. The first gate electrode structure extends in a second direction crossing the first direction.Type: GrantFiled: June 2, 2017Date of Patent: February 27, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Il Bae, Kang-Ill Seo
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Patent number: 9887226Abstract: An imaging device that includes a substrate, a photoelectric conversion section disposed in the substrate, an element isolation region disposed adjacent to the photoelectric conversion section, a floating diffusion electrically connected to the photoelectric conversion section, an amplification transistor having a gate electrode and an active region, and a contact section disposed on the gate electrode of the amplification transistor. The contact section overlaps the active region of the amplification transistor. The floating diffusion is electrically connected to the gate electrode of the amplification transistor via the contact section. The width of the gate electrode of the amplification transistor is larger than a width of the active region of the amplification transistor. The photoelectric conversion section includes a first type impurity, and the element isolation region includes a second type impurity having a conductivity opposite to the first type impurity.Type: GrantFiled: March 21, 2017Date of Patent: February 6, 2018Assignee: Sony Semiconductor Solutions CorporationInventor: Kazuichiro Itonaga
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Patent number: 9882092Abstract: Provided are a light emitting device, an electrode structure, a light emitting device package, and a lighting system. The light emitting device includes a light emitting structure layer comprising a first semiconductor layer, a second semiconductor layer, and an active layer. An electrode disposed on a top surface of the first semiconductor layer, a first layer includes a transmittive oxide material between the top surface of the first semiconductor layer and the electrode, and a second layer disposed is disposed between the first layer and the electrode, wherein the first layer is formed in a different material from the second layer, wherein the electrode comprises a lower portion connected to the first semiconductor layer and an upper portion on a top surface of the second layer.Type: GrantFiled: October 4, 2016Date of Patent: January 30, 2018Assignee: LG INNOTEK CO., LTD.Inventors: Kwang Ki Choi, Hwan Hee Jeong, Sang Youl Lee, June O Song
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Patent number: 9852940Abstract: A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after soldering, silver ions are not present and are not therefor free to migrate under the epoxy layer to form dendrites.Type: GrantFiled: January 31, 2013Date of Patent: December 26, 2017Assignee: Infineon Technologies Americas Corp.Inventors: Martin Standing, Andrew Sawle, Matthew P. Elwin, David P. Jones, Martin Carroll, Ian Glenville Wagstaffe
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Patent number: 9852939Abstract: A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after soldering, silver ions are not present and are not therefor free to migrate under the epoxy layer to form dendrites.Type: GrantFiled: January 30, 2013Date of Patent: December 26, 2017Assignee: Infineon Technologies Americas Corp.Inventors: Martin Standing, Andrew Sawle, Matthew P. Elwin, David P. Jones, Martin Carroll, Ian Glenville Wagstaffe
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Patent number: 9853161Abstract: A thin film transistor (TFT) is provided which is capable of reducing leakage currents in a polycrystalline silicon TFT without causing an increase in manufacturing processes. Source/drain regions of an activated layer of the TFT to be formed in a circuit region and pixel region formed on a glass substrate of a liquid crystal display panel for a mobile phone is formed so that its boron impurity falls within a range of 2.5×1018/cm3 to 5.5×1018/cm3 and its impurity activation falls within a range of 1% to 7%.Type: GrantFiled: March 19, 2010Date of Patent: December 26, 2017Assignee: NLT TECHNOLOGIES, LTD.Inventor: Kunihiro Shiota
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Patent number: 9831382Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer.Type: GrantFiled: December 3, 2012Date of Patent: November 28, 2017Assignee: Sensor Electronic Technology, Inc.Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Remigijus Gaska, Michael Shur
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Patent number: 9831341Abstract: The present disclosure provides many different embodiments of an IC device. The IC device includes a gate stack disposed over a surface of a substrate and a spacer disposed along a sidewall of the gate stack. The spacer has a tapered edge that faces the surface of the substrate while tapering toward the gate stack. Therefore the tapered edge has an angle with respect to the surface of the substrate.Type: GrantFiled: June 16, 2014Date of Patent: November 28, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shin-Jiun Kuang, Tsung-Hsing Yu, Yi-Ming Sheu
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Patent number: 9786637Abstract: There is presented a light emitting device, having plural light emitting elements disposed on a substrate, in which a protection element, such as a zener diode, can be disposed at an appropriate position. The light emitting device includes: a substrate; a light emitting section having plural light emitting elements disposed in a mounting area on the substrate; a positive electrode and negative electrode each having a pad section and wiring section to apply voltage to the light emitting section through the wiring sections; a protection element disposed at one of the positive electrode and negative electrode and electrically connected with the other one electrode; and a light reflecting resin formed on the substrate such as to cover at least the wiring sections and the protection element, wherein the wiring sections are formed along the periphery of the mounting area such that one end portions thereof are adjacent to each other.Type: GrantFiled: December 11, 2015Date of Patent: October 10, 2017Assignee: NICHIA CORPORATIONInventor: Haruaki Sasano
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Patent number: 9735153Abstract: A semiconductor device includes a first fin structure disposed on a substrate. The first fin structure extends in a first direction. A first sacrificial layer pattern is disposed on the first fin structure. The first sacrificial layer pattern includes a left portion and a right portion arranged in the first direction. A dielectric layer pattern is disposed on the first fin structure and interposed between the left and right portions of the first sacrificial layer pattern. A first active layer pattern extending in the first direction is disposed on the first sacrificial layer pattern and the dielectric layer pattern. A first gate electrode structure is disposed on a portion of the first active layer pattern. The portion of the first active layer is disposed on the dielectric layer pattern. The first gate electrode structure extends in a second direction crossing the first direction.Type: GrantFiled: July 14, 2014Date of Patent: August 15, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Il Bae, Kang-Ill Seo
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Patent number: 9736590Abstract: According to an embodiment, a microfabricated structure includes a cavity disposed in a substrate, a first clamping layer overlying the substrate, a deflectable membrane overlying the first clamping layer, and a second clamping layer overlying the deflectable membrane. A portion of the second clamping layer overlaps the cavity.Type: GrantFiled: June 6, 2014Date of Patent: August 15, 2017Assignee: Infineon Technologies AGInventors: Wolfgang Klein, Reinhard Gabl
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Patent number: 9721874Abstract: Pre-encapsulated lead frames suitable for use in microelectronic device packages are disclosed. Individual lead frames can include a set of multiple lead fingers arranged side by side with neighboring lead fingers spaced apart from each other by a corresponding gap. An encapsulating compound at least partially encapsulates the set of lead fingers without encapsulating a microelectronic device. The encapsulating compound can generally fill the plurality of gaps between two adjacent lead fingers.Type: GrantFiled: January 22, 2013Date of Patent: August 1, 2017Assignee: Micron Technology, Inc.Inventors: Ai Chie Wang, Choon Kuan Lee, Chin Hui Chong, Wuu Yean Tay
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Patent number: 9721859Abstract: A method of assembling a semi-hermetic semiconductor package includes bonding a semiconductor die having bond pads to a top side of a base region of a package substrate having vertical side walls that are hollow which define an inner open volume (gap) having an adhesive or thermoplastic material therein. There are a plurality of metal terminals providing top terminal contacts on the top side of the base region and bottom terminal contacts on a bottom side or below the base region. The bond pads are coupled to the top terminal contacts. A lid is placed which provides a top for the semiconductor package, where the lid extends to vertically oriented end protrusions so that the protrusions are positioned within the adhesive or thermoplastic material to secure the protrusions within the adhesive or thermoplastic material to provide a seal for the semiconductor package.Type: GrantFiled: September 1, 2015Date of Patent: August 1, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Andy Quang Tran, Alok Kumar Lohia, Reynaldo Corpuz Javier
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Patent number: 9716167Abstract: A trench DMOS transistor with a very low on-state drain-to-source resistance and a high gate-to-drain charge includes one or more floating islands that lie between the gate and drain to reduce the charge coupling between the gate and drain, and effectively lower the gate-to-drain capacitance.Type: GrantFiled: February 22, 2011Date of Patent: July 25, 2017Assignee: National Semiconductor CorporationInventors: Yaojian Leng, Richard Wendell Foote, Jr., Steven J. Adler
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Patent number: 9704831Abstract: A transistor chip formed from a wide band gap semiconductor, on which transistor elements for an upper arm are formed is mounted on a front surface of an insulating substrate. A transistor chip formed from a wide band gap semiconductor, on which transistor elements for a lower arm are formed is mounted on a rear surface of the insulating substrate.Type: GrantFiled: May 21, 2010Date of Patent: July 11, 2017Assignee: Mitsubishi Electric CorporationInventors: Akira Hatai, Shizuri Tamura