Abstract: Self-aligning photolithography method and a method of fabricating a semiconductor device using the same, in which the photolithography method is performed using a lower pattern without employing a separate mask. The self-aligning photolithography method includes the steps of forming a lower pattern layer on a semiconductor substrate, depositing a photoresist, and subjecting to exposure without a photomask such that the photoresist aligned with the lower pattern layer is not to be exposed by diffraction of light, and either removing or leaving only the photoresist aligned with the lower pattern layer by development.

Abstract: A ball-grid-array-type semiconductor device comprising a package substrate constituted with a ceramic wiring board having a semiconductor chip mounting portion on the principal plane and electrodes arranged like an array on the back, a semiconductor chip secured to the principal plane of the package substrate, connection means for electrically connecting the electrodes of the semiconductor chip with the wiring of the wiring board, a sealing body provided for the principal plane side of the wiring board and made of an insulating resin to cover the semiconductor chip and the connection means, a pedestal layer made of low-fusion-point solder and formed on the electrodes, and a metallic ball secured onto the pedestal layer; wherein a buffering layer made of high-fusion-point solder which covers the entire surface of the electrodes and whose margin extends up to a predetermined length on the back of the package substrate is formed on the electrodes and the pedestal layer is formed on the buffering layer.

Abstract: A method for planarizing a polycrystalline silicon layer deposited on a trench, which is formed on a semiconductor substrate, comprises the following steps. First, a polycrystalline silicon layer with an enough thickness is deposited on the surface of the semiconductor substrate to overfill the trench. At least one dimple is undesirably developed on the polycrystalline silicon layer during the polycrystalline silicon deposition. Then, an oxide layer with an enough thickness is formed on the polycrystalline silicon layer to overfill the at least one dimple. Next, the polycrystalline silicon layer is partially oxidized so as to transform the upper portion thereof into a polysilicon oxide layer. As a result of a non-uniform distribution of the oxidization rate, the bottom surface of the polysilicon oxide layer, i.e. the interface between the polysilicon oxide layer and the non-oxidized portion of the polycrystalline silicon layer, is substantially planar.

Abstract: A semiconductor device includes a first insulating film formed on a semiconductor substrate. Wiring patterns are partially formed on the first interlayer insulating film. A second insulating film is formed to cover the first insulating film and the wiring patterns. A third insulating film is formed on the second insulating film. In this case, at least an upper surface portion of the first insulating film has a moisture containing percentage lower than that of the second insulating film.

Abstract: A method for manufacturing a high dielectric capacitor is provided. A capacitor cell unit comprised of an amorphous, high dielectric film which is formed on a semiconductor substrate. Next, the amorphous high dielectric film is crystallized by annealing the capacitor cell unit under a non-oxidizing atmosphere.

Abstract: A method of making micro-actuator devices including a silicon wafer, a magnet positioned inside an insulated actuating chamber having electrical coil wound around its circumference thereby forming an electromagnet assemblage. A plurality of etched holes in silicon wafer receives the electromagnet assemblage and is adapted to produce a magnetic field in response to an applied current that acts on the magnet to cause the axial reciprocating motion of the magnet.

Abstract: A semiconductor device having grown oxide spacers and a method for manufacturing such a semiconductor device is provided. In one embodiment of the invention, a gate electrode is formed over a substrate, and an oxidation-resistant layer is formed adjacent to the gate electrode. The gate electrode is oxidized to grow an oxide layer on the gate electrode extending over the oxidation-resistant layer. One or more spacers then is formed adjacent to the gate electrode using the oxide layer.

Abstract: The present invention includes a method and system to increase the deep trench sidewall surface area in a storage node on a DRAM chip. By tilting the trenches the capacitance is increased without taking up more space on the semiconductor chip.

Abstract: An isolation structure on an integrated circuit is formed using a shallow trench isolation process. On a substrate, a trench is formed. A thermal anneal is performed to oxidize exposed areas of the substrate to provide for round corners at a perimeter of the trench. The thermal anneal in performed in an ambient where a chlorine source is added to O.sub.2 in order to minimize facets while creating the round corners. Oxidation time is lengthened by introducing an inert gas during the thermal anneal.

Abstract: A method is presented for forming a transistor wherein a silicide layer is formed upon an impurity region of a semiconductor substrate. After forming the silicide layer, a gate structure is preferably formed upon an exposed portion of the semiconductor substrate; however, the silicide layer may be formed after forming the gate structure. In order to form the gate structure, a layer of sacrificial material is first formed above the semiconductor substrate. An opening is then patterned through the layer of sacrificial material such that a portion of the semiconductor substrate is exposed. The gate structure preferably includes a metal gate conductor and a metal oxide gate dielectric.

Abstract: A barrier film 5 such as silicon oxide film or the like is formed on the back surface of a semiconductor substrate. Then, a copper-based metal film is formed on the principal surface of the semiconductor substrate. (Selected Drawing: FIG.

Abstract: In a DRAM, a plurality of memory cells each consisting of a memory cell selection transistor Qs and an information storage capacity element connected thereto in series are provided on a semiconductor substrate 1. An active region of the memory cell selection MISFET Qs is formed to have an isolated rectangular plan view. A part of the bit line BL extends in a direction crossing the extending direction thereof, and the extending part two-dimensionally overlaps a semiconductor region formed in the active region and is electrically connected thereto. In the DRAM having this structure, the bit line BL is formed of conductive films 16b1 and 16b2 embedded in the contact hole 14b for the bit line and in the wiring groove 15a for the bit line.

Abstract: A first embodiment of the present invention introduces a method to cure mobile ion contamination in a semiconductor device during semiconductor processing by the steps of: forming active field effect transistors in a starting substrate; forming a first insulating layer over the field effect transistor and the field oxide; forming a second insulating layer over the first insulating layer; and performing an annealing step in a nitrogen containing gas ambient prior to exposing the insulating layer to mobile ion impurities. A second embodiment teaches a method to cure mobile ion contamination during semiconductor processing by annealing an insulating layer in a nitrogen containing gas ambient prior to exposing said insulating layer to mobile ion impurities.

Abstract: A surface of a conductive member such as a gate electrode provided with a silicon layer is roughened. The roughened silicon layer is silicified so that its width is substantially increased, whereby phase transition of the silicide layer is simplified. Thus, the resistance of the refined silicide layer is reduced due to the simplified phase transition.

Abstract: The present invention is directed to a semiconductor device having an ultra thin gate oxide and a method for making same. The method is comprised of implanting nitrogen into a region of a semiconducting substrate, and forming a gate dielectric above the region in the substrate. The method further comprises forming a gate conductor above the gate dielectric and forming at least one source/drain region. The present invention is also directed to a transistor having a gate dielectric positioned above a surface of a semiconducting substrate, the gate dielectric being comprised of a nitrogen bearing oxide having a nitrogen concentration ranging from approximately 4-8%. The transistor further comprises a gate conductor positioned above the gate dielectric and at least one source/drain region.

Abstract: A method for planarizing metal plugs for device interconnections. The process begins by providing a semiconductor structure with at least one device thereon. A dielectric layer is formed over the device and the semiconductor structure. A first barrier metal layer is formed on the dielectric layer, and a sacrificial oxide layer is formed on the first barrier metal layer. The sacrificial oxide layer, the first barrier metal layer, and the dielectric layer are patterned to form contact openings. A second barrier metal layer is formed over the semiconductor structure, and a metal contact layer is formed on the second barrier metal layer. The metal contact layer and the second barrier metal layer are planarized using a first chemical mechanical polishing process and the sacrificial oxide layer is removed. The metal contact layer and the first barrier metal layer are planarized using a second chemical mechanical polishing process.

Abstract: An improved semiconductor device and method of manufacturing employs interconnecting films on film circuit as ground lines which extend to the periphery of the film circuit where there is a further connection to a conductive reinforcing plate 25. Advantageously, the conductive reinforcing plate reduces electrical noise from interfering with the semiconductor device and prevents the semiconductor device from radiating undesired signals. The interconnecting films also reduce cross-talk between signal lines of the semiconductor device.

Abstract: An effective barrier layer to chemical attack of fluorine during chemical vapor deposition of tungsten from a tungsten fluoride source gas is fabricated by the present invention. A titanium nitride conformal barrier film can be formed by in-situ nitridation of a thin titanium film. The substrate is placed in a module wherein the pressure is reduced and the temperature raised to 350.degree. C. to about 700.degree. C. A titanium film is then deposited by plasma-enhanced chemical vapor deposition of titanium tetrahalide and hydrogen. This is followed by formation of titanium nitride on the titanium film by subjecting the titanium film to an nitrogen containing plasma such as an ammonia, an N.sub.2 or an NH.sub.3 /N.sub.2 based plasma. Tungsten is then deposited on the film of titanium nitride by plasma-enhanced chemical vapor deposition.

Abstract: In a method for manufacturing a semiconductor device, an insulating layer is formed on a semiconductor substrate, and a refractory metal is formed layer on the insulating layer. Then, a first opening is perforated in the refractory metal layer, and a part of the insulating layer is etched by using the refractory metal as a mask. Then, a second opening is perforated in the refractory metal layer. The second opening is superposed onto the first opening and is larger than the first opening. Then, the insulating layer is again etched by using the refractory metal layer as a mask, so that a T-shaped opening is perforated in the insulating layer. Finally, a modified T-shaped gate metal electrode is formed on the insulating layer having the T-shaped opening.

Abstract: A method for forming semiconductor devices involves defining a pattern of microspheres on a first structure and transferring that pattern of microspheres to a semiconductor structure. The microspheres may then be used as a mask to define features on the semiconductor structure. In this way, it is possible to form semiconductor devices without necessarily using a stepper. This may result in substantial capital savings in semiconductor manufacturing processes.