Patents Examined by Viktor Simkovic
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Patent number: 6171879Abstract: An integrated circuit and method are provided for sensing activity such as temperature variations in a surrounding environment. The integrated released beam sensor preferably includes a switch detecting circuit region and a sensor switching region connected to the switch detecting circuit region. The sensor switching region preferably includes a fixed contact layer, a sacrificial layer on the fixed contact layer, and a floating contact on the sacrificial layer and having portions thereof overlying the fixed contact layer in spaced relation therefrom in an open switch position and extending lengthwise generally transverse to a predetermined direction. The floating contact preferably includes at least two layers of material. Each of the at least two layers have a different thermal expansion coefficient so that the floating contact displaces in the predetermined direction responsive to a predetermined temperature variation so as to contact the fixed contact layer and thereby form a closed switch position.Type: GrantFiled: December 29, 1998Date of Patent: January 9, 2001Assignee: STMicroelectronics, Inc.Inventors: Tsiu Chiu Chan, Melvin Joseph DeSilva
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Patent number: 6171874Abstract: A method of manufacturing semiconductor devices wherein images of non-defect anomalies are captured and stored with image data and linkage data in a database. The non-defect anomaly data is stored in database for later retrieval.Type: GrantFiled: February 9, 1999Date of Patent: January 9, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Paul J. Steffan, Allen S. Yu
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Patent number: 6171880Abstract: A method is provided for the manufacture of a convective accelerometer and tilt sensor device using CMOS techniques. An integrated circuit chip is produced which includes a silicon substrate having an integrated circuit pattern thereon including a heater element located centrally of the substrate and at least first and second thermocouple elements located on the substrate on opposite sides of the heater element. Thereafter, portions of the substrate surrounding and beneath the heater and thermocouple elements are etched away to suspend the element on the substrate and thus to thermally isolate the elements from the substrate. The substrate is etched up to the cold thermocouple junction of the thermocouple elements so the cold junction remains on the substrate.Type: GrantFiled: June 14, 1999Date of Patent: January 9, 2001Assignee: The United States of America as represented by the Secretary of CommerceInventors: Michael Gaitan, Nim Tea, Edwin D. Bowen, Veljko Milanovic
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Patent number: 6171933Abstract: The invention provides a semiconductor wafer cleaving method and apparatus which are used to obtain an ideal vertical cleaved plane of semiconductor wafers. A semiconductor wafer (1) having a scribing mark (2) inscribed on the surface is set on fulcrum members (6a and 6b). The fulcrum members (6a and 6b) are left-right symmetrical centering around the scribing mark (2) and parallel to the scribing mark (2). Fulcrum members (4a and 4b) are disposed left-right symmetrically centering around the scribing mark (2) and in parallel to the scribing mark (2) on the upper side of the semiconductor wafer (1). The fulcrum members (4a and 4b) are disposed outside the fulcrum members (6a and 6b). Load is applied from the fulcrum members (4a and 4b) side, wherein fulcrum forces are caused to operate from the respective fulcrum members (4a, 4b, 6a and 6b) onto the semiconductor wafer (1).Type: GrantFiled: October 26, 1999Date of Patent: January 9, 2001Assignee: The Furukawa Electric Co. Ltd.Inventors: Jie Xu, Kenji Suzuki
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Patent number: 6168964Abstract: A method of fabricating a semiconductor light emitting device includes fabricating semiconductor light emitting devices on a large scale by forming desirable end surfaces of resonators using an etching process. The method includes the steps of forming, on a base body, semiconductor layers for constituting a plurality of semiconductor light emitting devices; grooving the semiconductor layers formed on the base body in the direction from a front surface of the semiconductor layers to the base body, to form stripe-like grooves; and forming a semiconductor film in the grooves by epitaxial growth; wherein a side surface of each of the grooves, which side surface finally forms an end surface of a resonator of each of the semiconductor light emitting devices, is a crystal plane being later in epitaxial growth rate than a bottom surface of the groove.Type: GrantFiled: January 29, 1999Date of Patent: January 2, 2001Assignee: Sony CorporationInventor: Yuichi Hamaguchi
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Patent number: 6165873Abstract: This invention relates to a process for manufacturing a semiconductor integrated circuit device comprising hydrogen annealing where a silicon substrate on which a device structure is formed and an interlayer insulating film is deposited is annealed in an atmosphere of hydrogen, comprising removing a substrate material on a substrate surface opposite to the surface on which a device structure is formed (substrate rear face), to make the substrate thinner before the hydrogen annealing; and processing the rear face for removing damages due to crystal defects and scratches generated on the rear face. According to this invention, hydrogen annealing can improve device properties and reliability, regardless of a device structure on the substrate surface, and a semiconductor integrated circuit device can be manufactured in a higher yield.Type: GrantFiled: November 23, 1999Date of Patent: December 26, 2000Assignee: NEC CorporationInventor: Koji Hamada
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Patent number: 6162699Abstract: A method for effectively generating limited trench width isolation structures without incurring the susceptibility to dishing problems to produce high quality ICs employs a computer to generate data representing a trench isolation mask capable of being used to etch a limited trench width isolation structure about the perimeter of active region layers, polygate layers, and Local Interconnect (LI) layers. Once the various layers are defined using data on the computer and configured such that chip real estate is maximized, then the boundaries are combined using, for example, logical OR operators to produce data representing an overall composite layer. Once the data representing the composite layer is determined, the data is expanded evenly outward in all horizontal directions by a predetermined amount, .lambda., to produce data representing a preliminary expanded region.Type: GrantFiled: October 29, 1998Date of Patent: December 19, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Larry Wang, Nick Kepler, Olov Karlsson, Basab Bandyopadhyay, Effiong Ibok, Christopher F. Lyons
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Patent number: 6162716Abstract: A method of forming an amorphous-Si (.alpha.-Si) gate with two or more .alpha.-Si layers with mismatched grains. The first embodiment involves forming two or more amorphous silicon layers over the gate dielectric. The amorphous silicon layers are formed insitu (in a reactor chamber without removing the wafer from the chamber). An amorphous silicon layer is deposited by exposing the substrate to a Silicon containing gas (E.g., SiH.sub.4). The Si containing gas flow is stopped. The chamber is pumped down and back filled with an inert gas to remove said silicon containing gas. In the next insitu step, the Si containing gas is restarted thus depositing the next amorphous Si layer. This deposition and purge cycle is repeated the desired number of times to form two or more mismatched .alpha.-Si layers. In the second embodiment, after an .alpha.-Si layer is deposited, the wafer is etched, for example in an HF vapor or wet clean. Then the wafer is returned to the chamber and another .alpha.Type: GrantFiled: March 26, 1999Date of Patent: December 19, 2000Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chen-Hua Yu, Jih-Churng Twu
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Patent number: 6159815Abstract: In order to produce a MOS transistor with HDD profile and LDD profile, the HDD profile is firstly formed, followed by the LDD profile, in the area for the LDD profile in order to produce steep dopant profiles. The LDD profile is preferably produced by etching and in situ doped selective epitaxy.Type: GrantFiled: June 4, 1999Date of Patent: December 12, 2000Assignee: Siemens AktiengesellschaftInventors: Bernhard Lustig, Herbert Schafer, Martin Franosch
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Patent number: 6156638Abstract: The invention includes methods of restricting diffusion between materials. First and second different materials which are separated by a barrier layer capable of restricting diffusion of material between the first and second materials are provided. The barrier layer is formed by forming a first layer of a third material over the first material. A second layer of the third material is formed on the first layer. The second material is formed over the second layer of the third material. In another aspect, the invention relates to diffusion barrier layers. In one implementation, such a layer comprises a composite of two immediately juxtaposed and contacting, yet discrete, layers of the same material. In another aspect, the invention relates to integrated circuitry. In one implementation, a semiconductive substrate has a conductive diffusion region formed therein.Type: GrantFiled: April 10, 1998Date of Patent: December 5, 2000Assignee: Micron Technology, Inc.Inventors: Vishnu K. Agarwal, Garo J. Derderian
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Patent number: 6146929Abstract: In manufacturing a thin-film transistor on a glass substrate, a first thin film consisting of an amorphous silicon thin film is formed on the glass substrate, and a second thin film is formed on the first thin film. Then, this second thin film is etched to form a mask pattern. A dopant ion is doped into the first thin film through the mask pattern to form a source region and a drain region. The process of forming the mask pattern and the process of forming the source and drain regions are carried out continuously without exposing the substrate to the atmosphere.Type: GrantFiled: July 9, 1999Date of Patent: November 14, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Yasuhisa Oana, Kaichi Fukuda, Takayoshi Dohi
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Patent number: 6146951Abstract: A method of manufacturing a semiconductor device for preventing ESD damage is disclosed. A semiconductor device for preventing against ESD damage according to a first embodiment of the present invention, is fabricated as follows. Firstly, first impurity ions of a first conductivity type are implanted into a first region of a substrate of a semiconductor device using a first ion implantation, to form a first impurity ion layer. Here, a junction region will be formed in the first region and is connected to an input pad. Second impurity ions of the first conductivity type are then implanted into a second region of the substrate using a second ion implantation, to form a second impurity ion layer over the first ion impurity ion layer. Here, the second region includes the first region. Next, third impurity ions of a second conductivity type are implanted into the substrate of both sides of the first and second impurity ion layers, using a third ion implantation, to form a third impurity ion layer.Type: GrantFiled: June 24, 1998Date of Patent: November 14, 2000Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Deuk Sung Choi
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Patent number: 6143629Abstract: In a process for producing a semiconductor substrate, comprising sealing surface pores of a porous silicon layer and thereafter forming a single-crystal layer on the porous silicon layer by epitaxial growth, intermediate heat treatment is carried out after the sealing and before the epitaxial growth and at a temperature higher than the temperature at the time of the sealing. This process improves crystal quality of the semiconductor substrate having the single-crystal layer formed by epitaxial growth and improves smoothness at the bonding interface when applied to bonded wafers this process enables the detection of the smaller particles on the surface by a laser light scattering method.Type: GrantFiled: September 3, 1999Date of Patent: November 7, 2000Assignee: Canon Kabushiki KaishaInventor: Nobuhiko Sato
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Patent number: 6143582Abstract: The invention relates to device processing, packaging and interconnects that will yield integrated electronic circuitry of higher density and complexity than can be obtained by using conventional multi-chip modules. Processes include the formation of complex multi-function circuitry on common module substrates using circuit tiles of silicon thin-films which are transferred, interconnected and packaged. Circuit modules using integrated transfer/interconnect processes compatible with extremely high density and complexity provide large-area active-matrix displays with on-board drivers and logic in a complete glass-based modules. Other applications are contemplated, such as, displays, microprocessor and memory devices, and communication circuits with optical input and output.Type: GrantFiled: February 12, 1999Date of Patent: November 7, 2000Assignee: Kopin CorporationInventors: Duy-Phach Vu, Brenda Dingle, Ngwe Cheong
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Patent number: 6143583Abstract: The method of the present invention provides a process for manufacturing MEMS devices having more precisely defined mechanical and/or electromechanical members. The method of the present invention begins by providing a partially sacrificial substrate and a support substrate. In order to space the mechanical and/or electromechanical members of the resulting MEMS device above the support substrate, mesas are formed on the support substrate. By forming the mesas on the support substrate instead of the partially sacrificial substrate, the mechanical and/or electromechanical members can be more precisely formed from the partially sacrificial substrate since the inner surface of the partially sacrificial substrate is not etched and therefore remains planar. As such, trenches can be precisely etched through the planar inner surface of the partially sacrificial substrate to define mechanical and/or electromechanical members of the MEMS device.Type: GrantFiled: June 8, 1998Date of Patent: November 7, 2000Assignee: Honeywell, Inc.Inventor: Ken Maxwell Hays
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Patent number: 6140204Abstract: Ingredient gas is first supplied into a reacting section disposed in an apparatus for chemical vapor deposition. Subsequently, a silicon film is deposited on a wafer under a condition that temperature at the upstream side of a direction of the ingredient gas flow inside the reacting section is higher than that at the downstream side thereof.Type: GrantFiled: July 20, 1998Date of Patent: October 31, 2000Assignee: NEC CorporationInventor: Hirohito Watanabe
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Patent number: 6140146Abstract: Processes and apparatus for manufacturing radio frequency transponders having substrates formed from a flexible tape or film are disclosed. The RF transponders are formed on the tape so that their longest dimension (e.g., their length ("L")) is oriented parallel to the length of the tape. This layout places few or no constraints in the transponder's length allowing the length of the transponder's antenna circuit to be adjusted to satisfy the requirements of various applications.Type: GrantFiled: August 3, 1999Date of Patent: October 31, 2000Assignee: Intermec IP Corp.Inventors: Michael John Brady, Dah-Weih Duan, Harley Kent Heinrich
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Patent number: 6136667Abstract: A process for device fabrication is disclosed in which two substrates having different crystal lattices are bound together. In the process the substrate surfaces are thoroughly cleaned and placed in physical contact with each other. The duration of the contact and the pressure of the contact are selected to facilitate a bond between the two substrate surfaces that results from attractive Van der Waals' forces between the two surfaces. The bonded substrates are heated to a moderate temperature to effect escape of gases which may be entrapped by the substrates. The bulk of one of the substrates is then typically removed. The substrates can be heated again to a moderate temperature to effect removal of any gases remaining entrapped on the substrates. Thereafter, the bonded surfaces are heated to a high temperature to effect a permanent bond.Type: GrantFiled: August 5, 1999Date of Patent: October 24, 2000Assignee: Lucent Technologies Inc.Inventors: Sanghee Park Hui, Barry Franklin Levine, Christopher James Pinzone, Gordon Albert Thomas
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Patent number: 6136631Abstract: A microelectronic integrated sensor is formed with a cantilever. For the purpose of ensuring a system which is especially invulnerable to mechanical strains during production, the cantilever is placed freely movably on a support, and motion limiters are provided on the edge. The invention also provides for the formation of nitride pillars for supporting the upper layers, in order to further increase the stability. A corresponding production process for producing the sensor is disclosed as well.Type: GrantFiled: November 19, 1998Date of Patent: October 24, 2000Assignee: Siemens AktiengesellschaftInventors: Karlheinz Mueller, Stefan Kolb
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Patent number: 6136624Abstract: An array substrate typically used in a liquid crystal display device includes inter-layer insulating films thick enough to prevent step-off breakage of conductive layers at contact holes while promising a reliability. Thick inter-layer insulating films are made by stacking a film made of an inorganic material, such as silicon nitride or silicon oxide, having a low moisture permeability and thereby promising a reliability of the liquid crystal display device, and a film made of an organic material, such as acrylic resin, that can be readily stacked thick so that the inner wall of the contact hole is gently sloped with respect to the substrate surface to thereby prevent step-off breakage of a conductive layer as thin as 100 nm or less.Type: GrantFiled: March 9, 1998Date of Patent: October 24, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Masato Kemmochi, Masato Shoji