Abstract: A semiconductor memory device includes an active matrix provided with a semiconductor substrate, a transistor formed on the semiconductor substrate and isolation regions for isolating the transistor, a first metal line formed on top of the active matrix and extending outside the transistor, a capacitor structure formed over the transistor and a second metal line formed on top of the capacitor structure to electrically connect the capacitor structure to the transistor through the first and the second metal lines. In the memory device, forming the capacitor structure at the position over the transistor can reduce the cell size of the memory cell.

Abstract: A process for forming a color image sensor cell, in which a bonding pad structure is protected from exposure to alkaline developer solution, used for definition of color filter elements, and also used to open a contact hole to the bonding pad structure, has been developed. The process features the use of a passivation layer, comprised of an overlying silicon nitride layer, and an underlying silicon oxide layer, located on the top surface of the bonding pad structure. The passivation layer protects the underlying bond pad structure from alkaline developer solutions used to define overlying color filter elements, of the color image sensor cell. After definition of the color filter elements the contact hole opening to the bond pad is finalized using a dry etching procedure, applied to the passivation layer.

Abstract: A sandwich device was prepared by electrodeposition of an insoluble layer of oligomerized tris(4-(2-thienyl)phenyl)amine onto conducting indium-tin oxide coated glass, spin coating the stacked platinum compound, tetrakis(p-decylphenylisocyano)platinum tetranitroplatinate, from toluene onto the oligomer layer, and then coating the platinum complex with aluminum by vapor deposition. This device showed rectification of current and gave electroluminescence. The electroluminescence spectrum (&mgr;max=545 nm) corresponded to the photoluminescence spectrum of the platinum complex. Exposure of the device to acetone vapor caused the electroemission to shift to 575 nm. Exposure to toluene vapor caused a return to the original spectrum. These results demonstrate a new type of sensor that reports the arrival of organic vapors with an electroluminescent signal.

Abstract: Within a method for fabricating an microelectronic fabrication there is first provided a substrate employed within an optoelectronic microelectronic fabrication, where the substrate comprises an optoelectronic microelectronic device which is in electrical communication with a bond pad formed over the substrate. There is then processed, when fabricating the substrate to form the optoelectronic microelectronic fabrication, the substrate in the absence of optoelectronically transducable radiation, in order to attenuate corrosion of the bond pad. The method is particularly useful for forming a color filter sensor image array optoelectronic microelectronic fabrication comprising multiple photoresist based patterned colored filter layers.

Abstract: In a method of manufacturing a silicon-based thin film photoelectric converter, a crystalline photoelectric conversion layer included in the photoelectric converter is deposited by plasma CVD under the following conditions: the temperature of the underlying film is at most 550° C.; a gas introduced into a plasma reaction chamber has a silane-based gas and a hydrogen gas where the flow rate of the hydrogen gas relative to the silane-based gas is at least 50 times; the pressure in the plasma reaction chamber is set to 3 Torr; and the deposition speed is 17 nm/min in the thickness-wise direction.

Abstract: The object of the present invention is to develop a manufacturing process for fabricating thin film transistors by using a crystalline semiconductor film appropriately for the purpose, in which the crystalline semiconductor film is formed by using a catalyst which enables crystallization at a low temperature and is easily gettered. Low temperature crystallization is realized by introducing Cu, a catalyst, on the amorphous semiconductor film and performing a heat treatment. Cu is gettered by immersing the polycrystalline semiconductor film which slightly includes Cu into a chemical fluid selected from a group consisting of a chemical including oxygen namely sulfuric acid.

Abstract: In a method of etching an Al or Al alloy layer, an Al or Al alloy layer is formed on an underlying surface, the surface of the Al or Al alloy layer is processed with TMAH, a resist pattern is formed on the surface of the Al or Al alloy layer processed with TMAH, and by using the resist pattern as an etching mask, the Al or Al alloy layer is wet-etched.

Abstract: A multiple panel is manufactured having individual panels in each of which a sealing material surrounds a pixel region and peripheral driver circuit regions. At least a part of the sealing material in the respective panels is provided with seal openings to enable a liquid crystal material to be injected into the inside of the sealing material. A single or a plurality of injection holes leading to the seal openings to permit the liquid crystal material to pass are formed on a side among the peripheral portion of the multiple panel. Vacuum injection method is carried out in a vacuum chamber, and the liquid crystal material is injected into the inside of the sealing material of the respective panels over the pixel regions and the peripheral driver circuit regions from the injection hole through the seal openings of the respective panels. Thereafter, the multiple panel is separated into individual panels.

Abstract: The invention uses implantation, typically hydrogen implantation or implantation of hydrogen in combination with other elements, to a selected depth into a wafer with that contains one or more etch stops layers, treatment to split the wafer at this selected depth, and subsequent etching procedures to expose etch stop layer and ultra-thin material layer. A method for making an ultra-thin material layer bonded to a substrate, has the steps: (a) growing an etch stop layer on a first substrate; (b) growing an ultra-thin material layer on the etch stop layer; (c) implanting an implant gas to a selected depth into the first substrate; (d) bonding the ultra-thin material layer to a second substrate; (e) treating the first substrate to cause the first substrate to split at the selected depth; (f) etching remaining portion of first substrate to expose the etch stop layer, and (g) etching the etch stop layer to expose the ultra-thin material layer.

Abstract: An insulation film is formed on a first single crystal silicon substrate, e.g., a hydrogen anneal substrate, an intrinsic gettering substrate and an epitaxial substrate. Hydrogen implantation is carried out from a surface of this insulation film, thereby forming a hydrogen implantation region in the first single crystal silicon substrate. Then, by carrying out a thermal treatment at 400 to 500° C., voids are formed in the hydrogen implantation region, and the first single crystal silicon substrate is cleaved therefrom. Next, the surface of the insulation film and a surface of a second single crystal silicon substrate are laminated and then, they are subjected to a thermal treatment at 1,000° C. or higher. With this method, the adverse influence, on a device, of defects in the substrate can be reduced and a yield can be enhanced.

Abstract: The present invention is directed to provide a manufacturing method of a liquid crystal display having high transmittance and high aperture ratio, wherein the method is capable of decreasing process time and cost by reducing numbers of photolithography process steps.

Abstract: Disclosed herein is an apparatus and process for punching and placing inserts of electrolyte and other material into a substrate layer for a gas sensor. The insert can be the solid electrolyte, porous electrolyte or protective layer of a gas sensor. The substrate material is typically alumina. The apparatus punches a hole in the alumina substrate, and then, in one step, punches an insert of a second material, such as a solid electrolyte, into the previously formed hole, thereby forming a composite layer/insert.

Abstract: After a reinforcing plate is bonded to the lower surface of a semiconductor substrate having a major surface on which integrated circuits are formed, the reinforcing plate is cut in units of integrated circuit chips. A reinforcing member is formed from the reinforcing plate bonded to the lower surface of each integrated circuit chip.

Abstract: The present invention is a method for integrating an anti-reflection layer and a salicide block. The method comprises following steps: provide a substrate that is divided into at least a sensor area and a transistor area, wherein the sensor area comprises a doped region and the transistor area comprises a transistor that includes a gate, a source and a drain; forms a composite layer on the substrate, herein the composite layer at least also covers both sensor area and transistor area, and the composite layer increases refractive index of light that propagate from the doped region into the composite layer; performs an etching process and a photolithography process to remove part of the composite layer and to let top of the gate, the source and the drain are not covered by the composite layer; and performs a salicide process to let top of the gate, the source and the drain are covered by a silicate.

Abstract: A wafer treatment apparatus is divided into a working zone (S1) and a loading zone (S2) by a wall (2). A closed wafer cassette(3) has a cassette body 31 having a bottom wall provided witha normally closed valve (5). A vent pipe (51) has one end part projecting from a cassette table (6) disposed in the working zone (S1) and the other end part opening into the loading zone (S2). When the cassette (3) is placed on the cassette table (6), the vent pipe (51) wedges through an incision formed in the valve (5) into the wafer cassette (3) to enable the interior of the cassette (3) to communicate with the loading zone (S2). Consequently, the pressure difference between the interior of the cassette (3) and the loading zone (S2) is reduced to naught.

Abstract: In a method for manufacturing a pressure sensor, in which a semiconductor pressure sensing element is applied to an assembly segment of a lead grid, the semiconductor pressure sensing element is electrically connected to contact segments of the lead grid. The lead grid having the semiconductor pressure sensing element is inserted into an injection molding die, and then the semiconductor pressure sensing element, in the injection molding die, is surrounded by a housing made of injection molding compound. A structure is present in the injection molding die through which a pressure feed for the semiconductor pressure sensing element is left free from the jacket of injection molding compound. A stamp is arranged in the injection molding die so as to be separated by a gap from the side of the assembly segment that is facing away from the semiconductor pressure sensing element or from the side of the semiconductor pressure sensing element that is facing away from the assembly segment.

Abstract: An SRAM memory cell device is provide having a single transistor and a single RTD latch structure. The single transistor and RTD latch structure are formed on a very thin silicon layer, typically in the range of 250 to 300 Å thick, allowing for increased memory cell density over a given area. The RTD latch structure is a lateral RTD device, such that the outer contacting regions, the tunneling barriers and the central quantum well are formed side-by-side as opposed to being stacked on top of one another. This allows for formation of the memory cell device on very thin silicon layers. The layers can then be stacked to form memory devices for use with computers and the like. The memory device can be formed employing silicon-on-insulator (SOI) technology to take advantage of SOI device characteristics.

Abstract: A precision, micro-mechanical semiconductor accelerometer of the differential-capacitor type comprises a pair of etched opposing cover layers fusion bonded to opposite sides of an etched proofmass layer to form a hermetically sealed assembly. The cover layers are formed from commercially available, Silicon-On-Insulator (“SOI”) wafers to significantly reduce cost and complexity of fabrication and assembly. The functional semiconductor parts of the accelerometer are dry-etched using the BOSCH method of reactive ion etching (“RIE”), thereby significantly reducing contamination inherent in prior art wet-etching processes, and resulting in features advantageously bounded by substantially vertical sidewalls.

Abstract: A pair of thin film transistors formed in adjacent layers of polysilicon. The gate of the first TFT and the source, drain and channel regions of the second TFT are formed in the first polysilicon layer. The source, drain and channel regions of the first TFT and the gate of the second TFT are formed in the second polysilicon layer. A dielectric layer is interposed between the first and second polysilicon layers. The first TFT gate overlaps the second TFT drain region in the first polysilicon layer and the second TFT gate overlaps the first TFT drain region in the second polysilicon layer. In another aspect of the invention, two TFTs are incorporated into a SRAM memory cell.

Abstract: There is disclosed a method of recycling a delaminated wafer produced as a by-product in producing an SOI wafer according to a hydrogen ion delaminating method by reprocessing it for reuse as a silicon wafer, wherein at least polishing of the delaminated wafer for removing of a step in the peripheral part of the delaminated wafer and heat treatment in a reducing atmosphere containing hydrogen are conducted as the reprocessing. There are provided a method of appropriately reprocessing a delaminated wafer produced as a by-product in a hydrogen ion delaminating method to reuse it as a silicon wafer actually, and particularly, a method of reprocessing an expensive wafer such as an epitaxial wafer many times for reuse, to improve productivity of SOI wafer having a high quality SOI layer, and to reduce producing cost.