Abstract: In some aspects, a power supply system includes a plurality of power supply devices configured to be connected to an integrated circuit, where a power supply device of the plurality of power supply devices includes a voltage regulator configured to generate a rail voltage, and an internal diagnostic circuit. The internal diagnostic circuit is configured to detect activation of an enable signal to activate the plurality of power supply devices according to an activation power sequence, detect a rail violation of the activation power sequence in response to a value of the rail voltage at a first time, not satisfying a first condition defined by a voltage threshold, or at a second time, not satisfying a second condition defined by the voltage threshold. In response to the rail violation being detected, the internal diagnostic circuit is configured to activate an interrupt signal.

Abstract: Embodiments disclosed herein relate to split rail architecture for power supplies in a system, and more particularly, to providing isolation and control of a power supply. In an example, an integrated circuit device is provided that includes a device voltage supply, an input/output (I/O) voltage supply coupled to the device voltage supply, and a level shifter circuit coupled to the I/O voltage supply. The level shifter circuit includes a pair of cross-coupled p-type metal-oxide semiconductor field effect transistors (PMOS transistors), a pair of n-type transistors (NMOS transistors) coupled between the pair of cross-coupled PMOS transistors and a ground connection, and an inverter circuit coupled to the device voltage supply and the level shifter circuit. The level shifter circuit further includes a capacitor coupled to the pair of cross-coupled PMOS transistors and the ground connection and is in parallel with respect to a first one of the pair of NMOS transistors.

Abstract: When receiving power requirement for power control and performing power control of a target device in accordance with the received power requirement, based on power consumption for a performance of each component of the target device and a device configuration of the target device, power saving level management information is created, which respectively defines the performance of each component at each power saving level associated with each of a plurality of divided power consumption ranges of the target device, and based on a power consumption upper limit value or the power saving level of the target device designated as the received power requirement, the power saving level management information is referred to and the performance of each component is set to a performance of the power saving level according to the power requirement, respectively.

Abstract: During an initial bootup in a bootloader of an SOC, a random number that is unique to the device is stored in secured storage. During a first bootup, a two-dimensional random key is stored in secure storage for encoding the ENV parameters. During a second (subsequent) bootup, the ENV parameters that are current in unsecured storage are compared against the ENV parameters that previously existed in order to identify a mismatch. A remediation security action can be taken responsive to a mismatch between the baseline digest and a dynamic digest. Ultimately, an operating system can be loaded in the bootloader.

Abstract: A request to update first configuration data associated with a first tenant of a multi-tenant system is received. The first configuration data can be included in a first shard residing at a first node of the system. The first shard can also include second configuration data associated with a second tenant. Upon initiation of an operation to update the first configuration data at the first node in accordance with the first request, an anomaly associated with the update at the first node is detected. A request to access the second configuration data is received. A second node that includes a second shard that includes the second configuration data is identified. An operation is performed to provide the second tenant with access to the second configuration data at the second node before the anomaly associated with the update to the first configuration data is resolved.

Abstract: According to the embodiments, a nonvolatile memory device is configured to store a normal operating system, and store a bootloader. A host device is capable of initiating the normal operating system by using the bootloader. The host device is configured to determine whether a first condition is established based on information obtained from the nonvolatile memory device; and rewrite, when determined the first condition is established, the bootloader so that an emergency software is initiated when booting the host device. The emergency software is executed on the host device. The host device is capable of issuing only a read command to the nonvolatile memory device under a control of the emergency software.

Abstract: A solution for generating a clock using a quadrature delay can include a first plurality of in-phase (I) inverter pairs configured to output an I signal according to a first input and an inverted in-phase (inverted I) signal according to a second input, with a phase delay circuit coupled in parallel to each of the plurality of pairs. The solution can include a second plurality of quadrature (Q) inverter pairs configured to output a Q signal according to a third clock signal input and an inverted Q signal (inverted Q) according to a fourth clock signal input and a phase detector including a plurality of cells, each of which can receive at least one of the I signal, the inverted I signal, the Q signal or the inverted Q signal and include at least one or more transistors having a gate connected to a ground.

Abstract: A multilevel power converter includes a plurality of switches, a first DC link capacitor, a second DC link capacitor, and one or more processors configured to: generate, for a duty cycle of the multilevel power converter, a pulse width modulated pulse pattern in accordance with a reduced common mode voltage scheme; modify the pulse width modulated pulse pattern to render a modified pulse pattern; and cause the plurality of switches to implement the duty cycle based at least in part on the modified pulse pattern to render a common mode voltage pulse to balance voltages at the first DC link capacitor and the second DC link capacitor.

Abstract: Disclosed are various embodiments for provisioning client devices. An enterprise credential can be obtained from a provisioning service. A client device can send an enrollment request to a management service specific to the enterprise associated with the client device. The management service can send an enrollment response to the client device. Then, the client device can receive a provisioning package from the management service. Next, the computing device can then be configured based upon the enrollment response.

Abstract: A network interface device operates in a normal transmit operating mode in which the network interface device continually receives transmission symbols from a link partner via the communication link. The network interface device determines that receive circuitry of the network interface device is to transition to a low power mode in response to receiving a sleep signal from the link partner. The network interface device then operates according to a quiet/refresh cycle of the low power mode to conserve power. The quiet/refresh cycle corresponds to a time schedule that includes a refresh time window in which receive circuitry of the network interface device is to be powered to receive a refresh signal from the link partner Immediately after transmission of the sleep signal, the network interface device transitions to a quiet time window of the time schedule in which the network interface device ignores transmissions from the link partner.

Abstract: A controller of a storage system, includes a plurality of modules each including an intellectual property (IP) module and a core module, wherein, based on the IP module operating as a master for a first module of the plurality of modules, an idle clock of the first module is a first clock, wherein based on the core module operating as a master for a second module of the plurality of modules, an idle clock of the second module is a second clock, wherein a clock frequency of the first clock is greater than zero and smaller than a maximum clock frequency, and wherein a clock frequency of the second clock is zero.

Abstract: The present application relates to a control right handover method and apparatus for power management, a device, and a storage medium. The method includes: adding power management handover option hardware-controlled performance states (HWP) in a basic input output system (BIOS) power management interface; setting an option value corresponding to the power management handover option HWP as Native Mode; saving Native Mode to an intermediate struct; and modifying bits of target registers in a central processing unit (CPU) according to the intermediate struct, whereby a control right for power management is handed over from a BIOS to an operating system (OS), and the OS acquires the control right for power management.

Abstract: A method for determining a temperature of a component of an electric machine includes providing a plurality of trained neural networks, providing a current measurement of a plurality of operational parameters of the electric machine, and processing the operational parameters using the neural networks. The method further includes integrating output parameters issued by the neural networks over a time period, and issuing the integrated parameters as a temperature of the component.

Abstract: A network interface device operates in a normal operating mode in which the network interface device continually receives transmission symbols via a communication link. The network interface device determines that the network interface device is to transition to a low power mode, and in response transitions receiver circuitry to the low power mode. During a transition time period corresponding to determining that that the network interface device is to transition to the low power mode, the network interface device ignores signals received via the communication link.

Abstract: Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.

Abstract: Within an integrated circuit including a processor system and a data processing array, one or more kernels in the processor system are executed in response to a scheduling request from a host data processing system. The one or more kernels receive configuration data for implementing trace or profiling of a user design executable by a plurality of active tiles of the data processing array. Using the one or more kernels, selected tiles of the plurality of active tiles of the data processing array are configured with the configuration data to perform the trace or the profiling. Trace data or profiling data is generated through execution of the user design by the data processing array. The one or more kernels provide the trace data or the profiling data to the host data processing system.

Abstract: Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.

Abstract: In one embodiment, a network of SSDs includes a switch with a plurality of powered ports configured to be communicatively coupled to a controller and a host client and a plurality of SSDs configured to be communicatively coupled to the plurality of powered ports. The switch is configured to deliver up to a predefined power level to each of the plurality of SSDs via the plurality of powered port. Each of the plurality of SSDs consumes power. The controller is configured to manage the predefined power level for each of the plurality of SSDs by identifying the power consumed by each of the plurality of SSDs and allocating a new power level to each of the plurality of SSDs based on the power consumed by each of the plurality of SSD. In one embodiment, the switch and the plurality of SSDs are configured to occupy a server rack space.

Abstract: A memory device may include a pin for communicating feedback regarding a supply voltage to a power management component, such as a power management integrated circuit (PMIC). The memory device may bias the pin to a first voltage indicating that a supply voltage is within a target range. The memory device may subsequently determine that a supply voltage is outside the target range and transition the voltage at the pin from the first voltage to a second voltage indicating that the supply voltage is outside the target range. The memory device may select the second voltage based on whether the supply voltage is above or below the target range.

Abstract: A system comprises an integrated circuit die substrate; volatile memory electrically coupled to the integrated circuit die substrate; a first integrated circuit die element electrically coupled to the integrated circuit die substrate, the first integrated circuit die element comprising a first field programmable gate array (FPGA), and the first integrated circuit die element disposed adjacent to the volatile memory; a battery charger operable to receive power from a main power supply, the main power supply having an on state and an off state, wherein the main power supply is supplying power in the on state and not supplying power in the off state; and a battery module disposed on a top portion of the first integrated circuit die element, the battery module operable to receive power from the battery charger, and the battery module operable to supply power to the volatile memory at least when the main power supply is in the off state.