Abstract: A semiconductor device and a power-off method of the semiconductor device, the semiconductor device including a first power source group including first and second power sources, a second power source group including a third power source and a power sequence controller. The power sequence controller performs power-on operations and power-off operations of the first to third power sources. The power sequence controller starts a power-off operation of the first power source group at a first time, and starts a power-off operation of the second power source group when the power voltage of the first power source group becomes a first voltage or when a first reference time has passed from the first time.

Abstract: An application processor includes an application processor including a first processor configured to generate a control signal based on whether user data is changed, wherein the application processor is configured to implement a power manager which dynamically controls power provided to the first processor, in response to the control signal.

Abstract: A power throttling engine includes a register configured to receive a power throttling signal. The power throttling engine further includes a decoder configured to generate a vector based on a value of the power throttling signal. The value of the power throttling signal is an amount of power throttling of a device. The power throttling engine further includes a clock gating logic configured to receive the vector and further configured to receive a clocking signal. The clock gating logic is configured to remove clock edges of the clocking signal based on the vector to generate a throttled clocking signal.

Abstract: Described are mechanisms and methods for applying Machine Learning (ML) techniques for power management at different levels of a power management stack. An apparatus may comprise a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have a plurality of memory registers. The second circuitry may be operable to establish values for a plurality of features based on samples of values of the plurality of memory registers taken at one or more times within a range of time of predetermined length. The third circuitry may be operable to compare the plurality of features against a plurality of learned parameters for a reference workload.

Abstract: A passive cable adaptor for connecting a data source device with a display device is described. The adaptor has a packet-based interface connector at one end, the connector having a positive main link pin, a negative main link pin, a positive auxiliary channel pin, and a negative auxiliary channel pin. At the other end is a micro serial interface connector, wherein multimedia content is transmitted over the cable adaptor and electrical power is supplied over the cable adaptor simultaneously. The cable adaptor has an auxiliary and hot plug detect (HPD) controller utilized to map the auxiliary channel and HPD signals of the packet-based digital display to the micro serial interface ID signal.

Abstract: The present disclosure relates to a method for supplying blockchain computing power and a system thereof. The method comprises the steps of: receiving a computing power purchase request sent by a user-side terminal; generating purchase result data according to the computing power purchase request; scheduling a first blockchain server to provide users with computing service according to the purchase result data; when the first blockchain server stops serving, starting timing to obtain the target duration; judging whether the first blockchain server restarts the service when the target duration is less than the preset duration threshold, and obtaining a preset result; when the preset result is YES, improving the computing power of the first blockchain server correspondingly, so that the total service duration of the user and the actually obtained total computing power remain unchanged; when the preset result is NO, scheduling a second blockchain server to provide users with computing service.

Abstract: To enhance the scaling of data processing systems in a computing environment, a number of data objects indicated in an allocation queue and a first attribute of the allocation queue are determined, where the allocation queue is accessible to a plurality of data processing systems. A number of data objects indicated in the allocation queue at a subsequent time is predicted based on the determined number of data objects and the first attribute. It is determined whether the active subset of the plurality of data processing systems satisfies a criterion for quantity adjustment based, at least in part, on the predicted number of data objects indicated in the allocation queue and a processing time goal. Based on determining that the active subset of data processing systems satisfies the criterion for quantity adjustment, a quantity of the active subset of data processing systems is adjusted.

Abstract: A method for performing stutter of dynamic random access memory (DRAM) where a system on a chip (SOC) initiates bursts of requests to the DRAM to fill buffers to allow the DRAM to self-refresh is disclosed. The method includes issuing, by a system management unit (SMU), a ForceZQCal command to the memory controller to initiate the stutter procedure in response to receiving a timeout request, such as an SMU ZQCal timeout request, periodically issuing a power platform threshold (PPT) request, by the SMU, to the memory controller, and sending a ForceZQCal command prior to a PPT request to ensure re-training occurs after ZQ Calibration. The ForceZQCal command issued prior to PPT request may reduce the latency of the stutter. The method may further include issuing a ForceZQCal command prior to each periodic re-training.

Abstract: A loop-powered field device includes a plurality of terminals coupleable to a process communication loop and a loop control module coupled to one of the plurality of terminals and configured to control an amount of current flowing through the loop control module based on a control signal. A field device main processor is operably coupled to the loop control module to receive its operating current (I_Main) from the loop control module and is configured to provide the control signal based on a process variable output. A low power wireless communication module is operably coupled to the loop control module to receive its operating current (I_BLE) from the loop control module. The low power wireless communication module is communicatively coupled to the field device main processor. The low power wireless communication module has an active mode and a sleep mode.

Abstract: Disclosed are examples of apparatuses including memory devices and systems comprising memories sharing a common enable signal, wherein the memories may be put into different power modes. Example methods for setting the different power modes of the memories are disclosed. In some examples, different power modes may be set by issuing memory group-level commands, memory-level commands, or combinations thereof.

Abstract: Methods and systems for providing hardware compute resiliency by using a compute fabric that includes sensors and re-programmable data processing components.

Abstract: A power management system may provide power management recommendations to a computer system including a plurality of computing nodes (which may include processors, etc.), to cause the computing nodes to individually or collectively adjust power states or modes of respective processors to achieve power management of the computer system. The power management system may be provided with a power management framework that continuously utilizes direct and indirect service-level feedbacks to guide power management decisions. The power management system may employ a reinforcement learning algorithm to make power management decisions at a user level, and provide a fast decision overriding mechanism for platform events or service-requested performance boosts.

Abstract: Techniques for allocating power budget to a central processing unit (CPU) of a computing device are described. According to an example of the present subject matter, an unloaded component is detected. The unloaded component remains undetected upon completion of a boot process of the computing device. Thereafter, a power budget allocated to the unloaded component is determined. The power budget may be based on the thermal design power (TDP) of the computing device. Based on the power budget, a power configuration of the CPU is changed from a default power level to a high-performance power level, wherein the default power level corresponds to the TDP of the computing device and the high-performance power level is a power level above the default power level and upto a maximum power level of the CPU.

Abstract: In general, embodiments disclosed herein relate to using high bandwidth memory (HBM) in a booting process. In embodiments disclosed herein, a region of the HBM is set aside as an additional memory pool (also referred to as a pool) for drivers and/or other memory heap requests in the booting process. One or more embodiments maintain the existing memory pool below four GB, but provide an additional resource for drivers and heap requests.

Abstract: A distribution system 100 includes a data management apparatus 10 and a plurality of calculators 20 that execute machine learning. The data management apparatus 10 includes a data acquisition unit 11 that acquires information regarding training data held in a memory 21 of each of the calculators 20, from the calculators 20, and a data rearrangement unit 12 that determines training data that is to be held in the memory 21 of each of the calculators 20, based on characteristics of the machine learning processes that are executed by the calculators 20, and the information acquired from the calculators.

Abstract: A technique includes a first compute node of a cluster of nodes receiving a communication from a cluster maintenance node of the cluster instructing the first compute node to provide an installation image that is received by the first compute node to a second compute node of the cluster. The first node and the second node are peers. The technique includes sharing the first installation stream that communicates the image to the first compute node. Sharing the first installation stream includes, while the first compute node is receiving the first installation stream, the first compute node providing a second installation stream to communicate parts of the image received via the first installation stream to the second compute node.

Abstract: Embodiments support secure booting of an IHS (Information Handling System) based on validation of the secure assembly and delivery of the IHS. A validation process of the IHS is initialized that delays further booting of the IHS until detected hardware components of the IHS are validated. An inventory certificate is retrieved that was uploaded to the IHS during factory provisioning of the IHS. The inventory certificate includes an inventory that identifies hardware components installed during factory assembly of the IHS. A collected inventory of detected hardware components of the IHS is compared against the inventory from the inventory certificate in order to validate the detected hardware components of the IHS as the same hardware components installed during factory assembly of the IHS. When the comparison validates the detected hardware components of the IHS as only including factory assembled hardware, further booting of the IHS is allowed.

Abstract: A device may include a processor system and an array of data processing engines (DPEs) communicatively coupled to the processor system. Each of the DPEs includes a core and a DPE interconnect. The processor system is configured to transmit configuration data to the array of DPEs, and each of the DPEs is independently configurable based on the configuration data received at the respective DPE via the DPE interconnect of the respective DPE. The array of DPEs enable, without modifying operation of a first kernel of a first subset of the DPEs of the array of DPEs, reconfiguration of a second subset of the DPEs of the array of DPEs.

Abstract: A band-pass clock distribution circuit includes a clock tree circuit including at least one clock buffer circuit. The clock tree circuit may be configured to receive a first clock signal from a clock generator circuit and to generate a second clock signal based on the first clock signal. A band-pass filter may be configured to receive the second clock signal and to provide a third clock signal to one or more load circuits. The band-pass filter includes a filtering resonant network including a first inductor and a second inductor coupled to one another at a center tap. The filtering resonant network is configurable to resonate with a parasitic capacitance associated with the one or more load circuits. A portion of the band-pass filter is integrated with the clock tree circuit.

Abstract: A building management system for a building system includes a building system interface configured to receive building system data; a knowledge base configured to receive the building system data, the knowledge base providing a model of the building system, the model including semantic descriptions of the building system data, the semantic descriptions of the building system data being arranged in an ontology; and a user interface configured to access the knowledge base.