Abstract: Disclosed is a method of fabricating an integrated circuit (IC) using a multiple (N>2) patterning technique. The method provides a layout of the IC having a set of IC features. The method further includes deriving a graph from the layout, the graph having vertices connected by edges, the vertices representing the IC features, and the edges representing spacing between the IC features. The method further includes selecting vertices, wherein the selected vertices are not directly connected by an edge, and share at least one neighboring vertex that is connected by N edges. The method further includes using a computerized IC tool to merge the selected vertices, thereby reducing a number of edges connecting the neighboring vertex to be below N. The method further includes removing a portion of the vertices that are connected by less than N edges.

Abstract: Provided is a storage battery management device (10) including a price information acquisition unit (11) that acquires power purchasing price information indicating a power purchasing price for each time period of power supplied from an electric power system, a remaining discharge capacity information acquisition unit (12) that acquires remaining discharge capacity information indicating the amount of power that can be discharged to a load from a storage battery, and a discharging schedule generation unit (13) that generates a discharging schedule in which an upper limit of the amount of power discharged from the storage battery is determined for each of a plurality of discharging time periods divided for each unit time, using the power purchasing price information and the remaining discharge capacity information.

Abstract: A semiconductor device according to the present invention includes: a through via formed to penetrate a semiconductor substrate; first and second buffer circuits; a wiring forming layer formed in an upper layer of the semiconductor substrate; a connecting wiring portion formed in an upper portion of the through via assuming that a direction from the semiconductor substrate to the wiring forming layer is an upward direction, the connecting wiring portion being formed on a chip inner end face that faces the upper portion of the semiconductor substrate at an end face of the through via; a first path connecting the first buffer circuit and the through via; and a second path connecting the second buffer circuit and the through via. The first path and the second path are electrically connected through the connecting wiring portion.

Abstract: The disclosure relates to a method for verifying a printed pattern. In an example embodiment, the method includes defining sectors of at least a portion of the features in the reference pattern, determining a contour of the printed pattern, and superimposing the contour of the printed pattern on the reference pattern. The method also includes determining surface areas of sectors of the printed pattern that correspond to the sectors of the reference pattern and calculating one or more parameters as a function of at least one of the surface areas, the parameters being related to a single sector or to multiple sectors. The method additionally includes evaluating the parameters with respect to a reference value.

Abstract: According to an embodiment, a process simulator has a layout processing unit to extract vertex coordinates of a first graphic of a layout of a semiconductor device described in a layout file used for a simulation, an initial mesh generation unit to generate a first initial mesh passing through the vertex coordinates in a plane direction of the layout, and a simulator unit to execute a process simulation of the semiconductor device based on simulation data in which a process flow of the semiconductor device is described, the layout, and the first initial mesh.

Abstract: A system for charging at least one battery may include a power and data communication bus including a plurality of AC and DC power lines and data communication lines, and a plurality of modular ports coupled thereto. Charging power modules and an inverter module(s) may be coupled to respective modular ports of the power and data communication bus. A central controller may be configured to communicate with the charging power modules and the inverter module(s) through the data communication lines, identify the charging power modules and the inverter module(s) coupled to the modular ports, along with respective functions and power ratings associated therewith, and selectively control the charging power modules and the inverter module(s) based upon their identified functions and power ratings to charge the at least one battery via the DC power lines and provide AC power back to the AC source.

Abstract: In some embodiments, in a method performed by at least one processor, spaces among a plurality of layout segments is analyzed by the at least one processor to determine at least one first-type conflicted edge according to a first predetermined length. Spaces among the plurality of layout segments is analyzed by the at least one processor to determine a plurality of potential conflicted edges according to a second predetermined length different from the first predetermined length. At least one second-type conflicted edge is determined by the at least one processor according to the plurality of potential conflicted edges. If at least one odd-vertex loop is formed in the plurality of layout segments is checked by the at least one processor according to the at least one first-type conflicted edge and the at least one second-type conflicted edge to determine if a violation occurs in the plurality of layout segments.

Abstract: A vehicle may include a controller programmed to discharge and charge a battery according to battery terminal voltage values predicted for future time instants traversed by a leading edge of a temporal sliding window having a selectable period based on resistance and capacitance parameters representing the battery and a duration of the selectable period. The battery terminal voltage values may be further predicted based on a state of charge of the battery. The resistance parameters may include internal resistance. Some of the resistance and capacitance parameters may define an RC circuit. The battery terminal voltage values may be further predicted based on a voltage drop across the RC circuit.

Abstract: A portable power charger having an internal rechargeable battery includes a charger housing having at least one power connection port and a flashlight feature having at least one light source. The power connection port is operatively connected to the rechargeable battery and used for connecting the charger with an external power source, an electronic device, or both. The flashlight feature is also operatively connected to the internal battery. The charger housing takes the form of a fashion accessory that can be worn by the user, making the power charger readily available and accessible when needed to charge an electronic device when a standard power source is not available. The charger housing can be opened or folded to expose the power connection port for use, and closed or unfolded to hide the power connection port so as not to detract from the charger's use as a fashion accessory.

Abstract: An integrated circuit design tool includes a cell library. An entry in the cell library comprises a specification of the cell including a first transistor and a second transistor. The first transistor can include a first set of nanowires or 2D material strips arranged in parallel to form a channel structure, and a gate conductor disposed across the first set of nanowires or 2D material strips. The second transistor can include a second set of nanowires or 2D material strips arranged in parallel to form a channel structure, and a gate conductor disposed across the first set of nanowires or 2D material strips. The number of nanowires or 2D material strips in the first set can be different from the number of nanowires or 2D material strips in the second set, so that the drive power of the individual transistors can be set with finer granularity.

Abstract: A vehicle may include a controller programmed to charge and discharge a battery according to an upper power limit that is based on estimates of ion-concentration profiles in the battery. The controller may be programmed such that for a given state of charge and temperature of the battery, the upper power limit increases as the profiles flatten. The upper power limit may be further based on a difference between a predefined expected power capability limit at the given state of charge and a power capability limit estimated from a voltage output and current input associated with the given state of charge.

Abstract: An end point report for a design of an electronic circuit may be analyzed. Results of a static timing analysis run are loaded, a path from the loaded results is selected, and technology specific context data is provided. Additionally, a determination is made for every test point of the selected path of design quality parameters for determining a design problem area, and a determination is made for every design problem area, of a root cause by analyzing design problem area data in comparison to related ones of the technology specific context data.

Abstract: A controller of a vehicle may be programmed to charge and discharge a battery according to a state of charge derived from model parameters defining one of a series of RC circuits that characterize frequency response of the battery to input current and that each has a time constant proportional to another of the time constants, and a proportionality parameter indicative of proportional relationship between the time constants. The proportionality parameter may be such that a ratio of the resistances of the RC circuits is equal to a ratio of the capacitances of the RC circuits.

Abstract: An electrified vehicle includes a surface, an electric vehicle supply equipment (EVSE) system attachable to the surface, and a retention assembly configured to removably secure the EVSE system to the surface. The retention assembly includes a first segment affixed to the surface and a second segment affixed to the EVSE system.

Abstract: The present invention relates to a graphic user interface for a 3D board inspection apparatus. The graphic user interface includes an actual measurement image display area in which a 3D actual measurement image of an inspection target is displayed based on 3D actual measurement data for the inspection target on a board, and a dimension setup display area in which a dimension of the inspection target in CAD data, a dimension of the inspection target in the 3D actual measurement data and a recommend dimension of the inspection target based on the 3D actual measurement data are displayed. A first contour line of the inspection target based on the dimension of the inspection target in the CAD data and a second contour line of the inspection target based on the 3D actual measurement data is displayed with overlapping the 3D actual measurement image of the inspection target in the actual measurement image display area.

Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

Abstract: A method of determining if a layout design for fabricating a layer of features of an integrated circuit is N-colorable, comprising identifying a set of candidate cells among layout cells of a layout design. Each candidate cell of the set of candidate cells is one of the set of base layout cells, or one of the set of composite layout cells, and constituent layout cells of the one of the set of composite layout cells having been determined as N-colorable. Whether a first candidate cell of the set of candidate cell is N-colorable is determined. An abutment-sensitive conflict graph of the first candidate cell is generated when the first candidate cell is N-colorable and the first candidate cell is not the top layout cell.

Abstract: Embodiments disclosed herein may generate and transmit power waves that, as result of their physical waveform characteristics (e.g., frequency, amplitude, phase, gain, direction), converge at a predetermined location in a transmission field to generate a pocket of energy. Receivers associated with an electronic device being powered by the wireless charging system, may extract energy from these pockets of energy and then convert that energy into usable electric power for the electronic device associated with a receiver. The pockets of energy may manifest as a three-dimensional field (e.g., transmission field) where energy may be harvested by a receiver positioned within or nearby the pocket of energy.

Abstract: A method of making a wireless charging device for an electronic device includes printing a decoration layer on a surface of a glass or glass-ceramic substrate using a non-conductive ink. A coil is printed on the decoration layer, and an electromagnetic interference absorber layer is applied over the printed coil.

Abstract: The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout including a first main feature and a second main feature; determining that the first main feature includes has a curvilinear-based shaped; determining that the second main feature has a polygon-based shape; and mapping a first portion of the IC design layout that includes the first main feature onto a polar coordinate and mapping a second portion of the IC design layout that includes the second main feature on onto a Cartesian coordinate.