Abstract: For an integrated circuit (IC) that is designed to execute user defined operations after initialization, a sequencing circuitry in the IC that delays the start of the user design execution until a set of initial condition has been computed and propagated is provided. The sequencing holds the first group of circuits at an initial state while a second group of circuits computes and propagates a set of initial conditions based at least partly on the initial state of the first group of circuits. The circuits in the first group when being held disregard their inputs and do not change their outputs. The first group of circuits is released from its initial state after the second group of circuits has completed computation and propagation of the set of initial conditions. The circuits in the first group when released are freed to store or clock-in new inputs and produce new outputs in order to perform the user defined operations in conjunction with the second group of circuits.

Abstract: A method of circuit conception including performing static timing analysis on a circuit design to identify a first subset of the synchronous devices having at least one input path with a slack time below a first threshold; simulating the circuit design using one or more functional test patterns to identify a second subset of the synchronous devices for which the number of activations during the simulation is above a second threshold; selecting at least one synchronous device forming part of both of the first and second subsets; and modifying the circuit design to include, for each selected synchronous device, a detection circuit coupled to one or more inputs of the selected synchronous device.

Abstract: Methods and systems for checking a wafer-level design for compliance with a rule include determining whether each chip layout out of multiple chip layouts complies internally with one or more layout design rules. A tile area is determined, having a size that is based on the one or more layout design rules, that crosses a boundary between adjacent chip layouts and that leaves at least a portion of each chip layout uncovered. It is determined whether portions of the plurality of chip layouts inside the tile area comply with the one or more layout design rules. The chip layouts are modified, if chip layout area within the tile area fails to comply with the design rule, to bring non-compliant periphery chip regions into compliance.

Abstract: A system for performing slew-driven clock tree synthesis includes pair selection and cost metric definition considering physical distance for efficient sink clustering; slew and skew-aware merging point computation for routing; and slew and insertion slew-aware net splitting.

Abstract: A method to adjust transistor gate geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to form a reticle. A method to adjust transistor geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to compensate for transistor turn on voltage drop off where the transistor gate crosses the isolation/active interface.

Abstract: A device having a design conversion from a field programmable gate array (FPGA) to an application specific integrated circuit (ASIC), comprising: a user configurable element in the FPGA replaced by a mask configurable element in the ASIC, wherein the FPGA and the ASIC have identical die size and identical transistor layouts.

Abstract: A charging device for inductive transfer of electric energy with a primary conductor arranged in a first housing, by which an alternating magnetic field can be generated when it is energized with an alternating current, electrically connected to a power source that is electrically connectable to a power electronics device for energizing the primary conductor with an alternating current. A drive means for moving the first housing from a first position to a second position, wherein the charging device is equipped with a fault detecting device, by which can be detected whether the first housing is or is not moved when a movement operation has been initiated by the drive means.

Abstract: Methods are disclosed to determine if wiring resources are available in the neighborhood of a physically routed net in all three dimensions. Such a method can select a wire trait based on an amount of usage of each wire segment in the net and the total percentage usage of the net. The method can also re-route a net using new wiring resources after determining that wiring resources are available. The new resources can provide improved RC (delay) characteristics and reduced signal coupling. The method can be applied to a VLSI design with multiple fails.

Abstract: Rendering a graphical representation of an integrated circuit can include determining, using a processor, a tile of a device model at least partially within a viewport, determining, using the processor, an owning tile having a fly-over wire passing over the tile, determining, using the processor, a predetermined shape of the fly-over wire, and drawing, using the processor, the fly-over wire within the viewport based upon the shape.

Abstract: Techniques for logic gate simulation. Program instructions may be executable by a processor to select logic gates from a netlist that specifies a gate-level representation of a digital circuit. Each logic gate may be assigned to a corresponding element position of a single-instruction, multiple-data (SIMD) shuffle or population count instruction, and at least two logic gates may specify different logic functions. Simulation-executable instructions including the SIMD shuffle or population count instruction may be generated. When executed, the simulation-executable instructions simulate the functionality of the selected logic gates. More particularly, execution of the SIMD shuffle or population count instruction may concurrently simulate operation of at least two logic gates that specify different logic functions.

Abstract: System design using accurate performance models may include generating, using a processor, a performance verification testbench from a hardware description language design and an automaton and determining, using the processor, a parameter of the design by analyzing the performance verification testbench using formal verification methods. The parameter is provably accurate. A performance model of a system under design including the design may be executed. The performance model uses the parameter. A determination may be made, using the processor, whether the system under design meets a system requirement according to a comparison of a result of executing the performance model with the system requirement.

Abstract: A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of numerous waveforms without simulating the individual waveforms. The design tool can determine an input sequence of signal transition representations associated with an input net of a component in RTL circuit design, where each signal transition representation represents a nondeterministic transition from a previous signal state to possible signal state(s). Determining the input sequence of signal transition representations includes determining that the input sequence of signal transition representations indicates an input gated clock waveform. The design tool also can determine, based on the indicated component and on the input gated clock waveform, an output sequence of signal transition representations derived from the input sequence of signal transition.

Abstract: A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of numerous waveforms without simulating the individual waveforms. The design tool can determine two or more input sequences of signal transition representations associated with an input net of an indicated component in an RTL circuit design, where the two or more input sequences of signal transition representations are associated with a mode element. Each signal transition representation represents a nondeterministic transition from a previous signal state to possible signal state(s). The mode element indicates a selection between two or more output sequences of signal transition representations. It is determined, based on the indicated component and the mode element, two or more output sequences of signal transition representations derived from the input sequence(s) of signal transition representations.

Abstract: In a general aspect, a quantum process for execution by a quantum processor is generated. In some instances, test data representing a test output of a quantum process are obtained. The test data are obtained based on a value assigned to a variable parameter of the quantum process. An objective function is evaluated based on the test data, and an updated value is assigned to the variable parameter based on the evaluation of the objective function. The quantum process is provided for execution by a quantum processor, and the quantum process provided for execution has the updated value assigned to the variable parameter.

Abstract: A system, methods, and a computer program product for estimating a yield and creating corners of a circuit design with the aid of a failure boundary classification. The system, methods and computer program product provide for determining, based on how many sampling factors have failures, whether data samples are sufficient as input to scaled-sigma sampling. If the data samples are insufficient, the failure boundary classification is usable to determine whether the yield is high enough to meet a yield target. A design corner can be located by applying a binary search to results of scaled-sigma sampling. The failure boundary classification can aid in setting up the search.

Abstract: An apparatus for controlling charging of an electric vehicle includes a switch unit including a first relay and second relays, wherein the first relay is arranged on an electric line through which a first battery is connected in series to a second battery. The first and second batteries supply driving power of the electric vehicle. The plurality of second relays is arranged on charging lines through which charging power is supplied to the first battery and the second battery, respectively. Further, a control unit configured to control the first relay and the plurality of second relays such that the first relay is turned off and the plurality of second relays is turned on to supply the charging power of a charger connected to a charging terminal to the first battery and the second battery, respectively, when the first battery and the second battery are charged.

Abstract: Methods for debugging a failure in a logic circuit design simulation by tracing a X-value are provided. In one aspect, a method includes detecting during a X-propagation logic circuit design simulation a failure at a register transfer level of a logic circuit comprising one or more logic blocks and tracing a X-value in a data path of the one or more logic blocks until the X-value is observed in a control path of the one or more logic blocks. The method also includes identifying a logic block comprising a control signal of the control path in which the X-value is observed, and identifying the logic block in which the X-value is observed as a root cause of the failure. Systems and machine-readable media are also provided.

Abstract: A method for compensating pattern placement errors during writing a pattern on a target in a charged-particle multi-beam exposure apparatus including a layout generated by exposing a plurality of beam field frames using a beam of electrically charged particles, wherein each beam field frame has a respective local pattern density, corresponding to exposure doses imparted to the target when exposing the respective beam field frames. During writing the beam field frames, the positions deviate from respective nominal positions because of build-up effects within said exposure apparatus, depending on the local pattern density evolution during writing the beam field frames.

Abstract: An electronic device and a method thereof, which supports fast wireless charging, are provided.

Abstract: A method, system, and computer program product for performing incremental common path pessimism analysis in integrated circuit design includes performing common path pessimism removal (CPPR) analysis to provide timing credit for one or more paths that are subject to common path pessimism. The method also includes identifying one or more post-CPPR critical paths based on the CPPR analysis, setting flags for critical nodes of the one or more post-CPPR critical paths, performing a design fix to address the one or more post-CPPR critical paths, and applying a set of rules based on the design fix and the flags to identify seed points among the critical nodes of the one or more post-CPPR critical paths. Invalidating and re-performing the CPPR analysis is done only for paths associated with the seed points.