Abstract: The invention relates to a method for modeling an input/output cell located on the perimeter of an integrated circuit. A method is taught to model an the integrated circuit when sufficient area is not available on the perimeter of the integrated circuit. The input/output cell can be modeled in two locations; one location on the perimeter of the cell and a second location in the interior area, or core, of the integrated circuit. The model uses a cover to prevent the area of the core of the integrated circuit from being used for other purposes. When the input/output cell is divided into a main cell and more than one pre-cell, the model uses a cover for each pre-cell. The model adjusts the timing of the signals to compensate for the input/output cell being divided into two areas. In an embodiment a software tool performs the functions of the model.

Abstract: In an illustrative embodiment, a desired signal processing transfer function is implemented using a generic pipelined data processor having variable latency followed by a variable latency multistage FIFO. The delay of the multistage FIFO is varied dynamically to keep the number of outstanding samples (and thus the overall latency) a constant. The present invention enables an abstract approach to the design of higher-level signal processing transfer functions while the design of the underlying low-level circuitry is driven solely by target implementation technology issues. Thus, the higher-level design of signal processing transfer functions is decoupled from the low-level (logic and physical) design. Furthermore, test bench modules and vectors for testing the transfer function can also be to be prepared independent of the specifics of the low-level circuitry associated with the target implementation technology.

Abstract: A system design support system is disclosed, which handles specifications at system level, e.g., a specification of software executed by a computer, specification of hardware implemented by combining semiconductor devices and the like, a specification of an incorporated system implemented by combining software and hardware, and a specification of a business process such as a workflow. This apparatus searches for an advertisement in accordance with an query specification. The apparatus also creates a communication procedure between the query specification and a specification of an advertisement part obtained by a search.

Abstract: A method of and an apparatus for performing efficient software emulation of a multi-processor target computer by a host computer. The software technique permits multiple processors to be emulated by a single processor. The use of software emulation permits the host computer to execute both host programs and target programs. The software emulation is made particularly efficient by utilizing the operation code combined with a separate four bit field to directly address the corresponding host instructions.

Abstract: A method and structure for simulating a circuit comprising inputting, from a customer site, initial memory states, and initial input signals to core logic within a host site, simulating the circuit utilizing the host site and the customer site connected though a wide area network (wherein the host site contains the core logic and the customer site contains customer logic, the core logic and the customer logic forming the circuit), comparing test output signals with the desired output signals, and altering the customer logic until the test output signals are consistent with the desired output signals.

Abstract: A computer system includes a printed circuit board manufactured in accordance with simulated trace impedances and topologies. The printed circuit board includes trace impedances characterizing at least three dimensions of a multi-dimensional space of the printed circuit board. The printed circuit board design includes trace impedances and topologies obtained with the use of a quasi-Monte Carlo simulation methodology.

Abstract: Design spaces for systems, including hierarchical systems, are programmatically validity filtered and quality filtered to produce validity sets and quality sets, reducing the number of designs to be evaluated in selecting a system design for a particular application. Validity filters and quality filters are applied to both system designs and component designs. Component validity sets are combined as Cartesian products to form system validity sets that can be further validity filtered. Validity filters are defined by validity predicates that are functions of discrete system parameters and that evaluate as TRUE for potentially valid systems. For some hierarchical systems, the system validity predicate is a product of component validity predicates. Quality filters use an evaluation metric produced by an evaluation function that permits comparing designs and preparing a quality set of selected designs. In some cases, the quality set is a Pareto set or an approximation thereof.

Abstract: There is disclosed a method of communicating with an integrated circuit chip having plural components thereon, the components including digital processing circuitry and an on-chip emulator connected to the digital processing circuitry for initiating command and control sequences for the digital processing circuitry in response to externally applied signals or in response to detected states of the digital processing circuitry.

Abstract: Collimated visual display apparatus comprising an aspheric screen (12) and a curved collimating mirror (16), characterised in that the aspheric screen (12) is not a surface of revolution about an axis, the aspheric screen (12) comprises first and second parts (6, 8) which are separated from each other by a third part (10), the first and second parts (6, 8) are curved in cross section and if connected together then they would form a surface of revolution, the third part (10) is straight in cross sectional view and is a short cylindrical centre section, and the collimated visual display apparatus is such that the aspheric screen (12) has an outer curved surface that is viewed via the curved collimating mirror (16) by a user of the collimated visual display apparatus.

Abstract: A simulation system is described for computing the overall signal generated in a substrate by a digital system comprising a plurality of gates associated with the substrate, wherein each gate is configured to perform a switching event. Output of a transistor-level model is compared with output of a lumped circuit model for each gate and the substrate, and signal contributions from each gate and switching event are determined based on the comparison. The system determines switching event signals for each of the plurality of gates. The signal contributions and the switching event signals are combined, and a combined lumped circuit model is derived based on a combination of lumped circuit models of the plurality of gates. The overall signal is computed based on the combined gate signal contributions and switching event signals, which are configured as an input to the combined lumped circuit model.

Abstract: A method, system, and data structure for instrumenting a cross-hierarchical simulation event are disclosed herein. The cross-hierarchical simulation event is a function of a first simulation event residing at a first level of simulation model hierarchy and a second simulation event residing at a second level of simulation model hierarchy. In accordance with the present invention, a cross-hierarchical instrumentation entity is defined within the first level of simulation model hierarchy utilizing an instrumentation declaration comment containing data representing a cross-hierarchical instrumentation entity. A first input of said instrumentation entity is connected to the first simulation event and a second input of the instrumentation entity is connected to the second simulation event utilizing an input port mapping comment that declares the cross-hierarchical instrumentation entity to generate a cross-hierarchical simulation event.

Abstract: A method and apparatus for clock generation and distribution in an emulation system is described. The present invention provides a method and apparatus for generating a derived clock signal with a circuit having a look up table. A counter circuit counts clock cycles and provides an index into the look up table. A frequency divider circuit may be used between the counter circuit and a base clock signal to provide an intermediate clock signal with a frequency that is less than the frequency of the base clock signal. In one embodiment, a selection circuit is provided to select between the base clock signal and an external clock signal.

Abstract: A method of and apparatus for determining whether a multi-component target system meets a given multi-part performability requirement is provided. A description of the target system, failure probabilities for components of the target system and a multi-part performability requirement for the target system are obtained. The multi-part performability requirement indicates desired performance levels and corresponding fractions of time. One or more failure-scenarios are successively computed that represent one or more states of the target system having zero or more components failed and a corresponding probability of occurrence of the one or more of the states of the target system. Performance of the target system is modeled under the failure scenarios using a performance predictor module for generating a multi-part performability function.

Abstract: The process is intended to optimize the operation of a digital protection system for protecting sets of busbars in the power station and uses a basic schematic of the electrical configuration of the power station obtained from information on the type of components used in the power station, and on the possible connections and accesses to said components. The information is assigned to management units of the digital protection system, said management units comprising peripheral measurement units and at least one centralization unit. A topological compilation process is implemented to provide a compiled schematic topology, and to provide a compiled assignment topology of the components in the power station and of their connections to the management units. A partial graph, whose structure depends on the type of information searched for and the status of each component of the power station, is obtained for each peripheral unit.

Abstract: Method and apparatus determine the performance of an integrated circuit that includes at least one of a plurality of deep-well trench dynamic random-access memory (DRAM) cells. The method includes executing a circuit simulator for designing an integrated circuit that contains at least one of a plurality of DRAM cells. Further, the method includes calculating a set of output parameters with the circuit simulator for each of the plurality of DRAM cells utilizing, for example, a deep-well trench DRAM cell model for each of the plurality of DRAM cells.

Abstract: An oilfield data analysis system is based on a four-tier software model which includes a “shared earth model” and a federation of “directory services”. The first tier is a universal graphical user interface (GUI) which can operate on any inexpensive computer as well as on an expensive workstation, i.e. a “web browser”. The second tier is an application server which is coupled to users via the worldwide web and serves geoscientific software applications. The third tier is a geometric modelling system where geometric data is stored and processed. The third tier embodies the “shared earth model”. The fourth tier is a database management system where non-geometric data is stored. According to the invention, there can be (and preferably are) multiple instances of each tier. Communication of data between different tiers is accomplished via XML data exchange.

Abstract: A method for designing high performance products incorporating signal processing and feedback control is disclosed. In one embodiment, a block diagram may be used for a design cycle, for design optimization, or for design estimation. The block diagram contains a set of differential equations or difference equations, and the solution of these sets of equations may be performed by commercially available software tools. In order to utilize the software tools without requiring access to source code or other descriptions of the internal structure of the tools, the system is decomposed using the technique of waveform relaxation. The decomposition using waveform relaxation operates directly to speed up the computations for the block diagram system. The remaining interprocessor communications may be held pending until the end of each iteration's calculations in each block, allowing the software tools to be executed on independent multiple processors.

Abstract: Matrix element calculation carried out efficiently without the overhead of communication between a host computer and processor elements even in parallel calculation utilizing a low-cost communication device and multiple processor elements having memories of a small capacity. In a method for calculating molecular orbitals, for example, all elements F(I, J) of a Fock matrix are calculated where an outermost loop is a loop associated with combinations (RT) of contracted shell R and contracted shell T which satisfy relationships R≦Nshell and T≦R. A second loop is a loop associated with contracted shell S, and a third loop is a loop associated with contracted shell U. Alternatively, the second loop is a loop associated with the contracted shell U, and the third loop is a loop associated with the contracted shell S. The value of S ranges from 1 to R, and the value of U ranges from 1 to R.

Abstract: The system for simulating user activity on a multi-tier computer network includes an event capture database for capturing interface level information and kernel level information associated with the interface level information. A virtual script editor module creates a virtual script from the captured interface level information and captured kernel level information to simulate user activity on the network. A virtual script playback module is responsive to the virtual script to produce virtual kernel level information indicative of network and server activity associated with a virtual user.

Abstract: A method of simulating the electrical behavior of an ideal transformer. The representation of the ideal transformer is frequency independent and can be used to simulate the behavior of an ideal transformer over the frequency range from DC to infinity. In one embodiment, the ideal transformer is represented as having an input sub-circuit and an output sub-circuit. Each sub-circuit includes a resistor connected in parallel across a current controlled current source. The input current, output current, current sources, and resistances are scaled by a scaling factor representing the turns ratio between the primary and secondary windings of a physical transformer. In the present invention, the current sources are responsible for the current scaling and the resistors are responsible for the impedance scaling. The circuit elements of the representation may be used as the basis for generating a set of input parameters for a circuit emulation program.