Abstract: A device and method identify and compensate for tensile and/or shear stress due to heat-caused expansion and contraction between an integrated heat spreader and thermal interface material. This device and method may change the shape of the integrated heat spreader based upon the identification of location(s) of high tensile and/or shear stress so that additional thermal interface material may be deposited between the integrated heat spreader and a die in corresponding locations. Utilizing this method and device, heat is efficiently transferred from the die to the integrated heat spreader.

Abstract: A process of designing a screenless completion for an oil or gas well includes selecting an oil or gas well having known characteristics and inputting data about them into a computer; determining, through operation of the computer, whether a screenless completion should be performed on the selected well and, if so, identifying materials to be used in the screenless completion and in response indicating to a user a screenless completion design using the identified materials. Different types of screenless completion designs are made available. These steps can be performed for multiple wells, preferably with similar results for similar wells.

Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.

Abstract: A modelling tool for use in defining an ASP which receives as its input an input file which for each of a set of peripherals defines the functional attributes of that peripheral in a high level language with an input data structure and which generates from the input file, (i) an interface functions file, which defines the communication attributes of the peripheral with the processor and the functional attributes of the peripheral in a manner independent of any particular data structure, (ii) a test functions file which defines the communication attributes of the processor with the peripheral in a manner independent of any particular data structure, and (iii) a register definition file by allocating specific elements of the input data structure to predefined sectors of a register definition table.

Abstract: The present invention provides a method and mechanism for simulating complex digital circuits using hybrid control and data flow representations. Specifically, the invention provides a method of simulating a digital circuit in such a way that the simulation is stopped at desired functions for subsequent analysis. A hardware design code describing the digital circuit is converted to an assignment decision diagram (ADD) representation that is then annotated with one or more control nodes that are used for maintaining control flow through a simulator. In this way, one or more break points are created that allow the simulator to stop at associated points in the simulation.

Abstract: A computer implemented process prescribes second-order tetrahedral elements during simulation in the design analysis of structure. The computer implemented process includes the steps of defining a finite element model for an element including at least one tetrahedral element, and defining the at least one tetrahedral element as a combination of hexahedral sub-elements. The computer implemented process also includes the steps of executing the simulation, and evaluating the structure for structural integrity responsive thereto.

Abstract: A method and apparatus are provided for accessing, viewing and manipulating data stored in a computer system. This is achieved by selecting one or more of the non-modifiable data objects stored in a computer system, creating references to the selected objects and adding the references to a reference list. The reference list is then manipulated to allow a user to add to, remove from or search the references in the reference list. In some embodiments, different operations are performed by different computers connected to a computer network such as the Internet. In such cases, data objects are stored on a server computer and searched by client computers connected to the server computer over the network. A reference list is stored on the client computers and can be directly manipulated by the user without a need for further interaction with the server computer.

Abstract: An average cache hit ratio and execution time not considering any interrupt are obtained by processes (1001-1011). A section hit ratio simulation (2006a) is done using the obtained information, interrupt generation probability information (2005), and cache scheme/cache size information (2004). A stall penalty (2008) is added to the obtained trace information (D) to attain the number of execution clocks, and the cache hit ratio and execution time are estimated. An average cache hit ratio and execution time considering an interrupt can be obtained.

Abstract: A spacecraft emulation system that can emulate both the attitude control subsystem and the non-attitude control subsystem is integrated into a single compact unit. The unit includes an emulated spacecraft control processor for processing attitude control information and an emulated central command and telemetry unit for interfacing simulated spacecraft data. The inlet also includes a first simulation engine that is operative to simulate the spacecraft attitude control system and a second simulation engine that is operative to simulate the spacecraft power, thermal, propulsion and payload subsystems. Both the first and second simulation engines are connected to the emulated spacecraft control processor via a respective bus. A host computer provides the command data and receives the telemetry data from the emulated spacecraft control processor.

Abstract: A method and apparatus for validating SoC (system-on-a-chip) design with high accuracy and speed and low cost. The [apparatus allows to use a] method [which] includes the steps of verifying individual cores to be integrated in an SoC by evaluating a silicon IC having a function and structure identical to that of each core constituting the SoC with use of test patterns generated based on simulation testbenches produced through a design stage of the cores; verifying interfaces between the individual cores, on-chip buses of the cores and glue logic by using the silicon ICs and simulation testbenches [developed by an SoC designer] and FPGA/emulation of the glue logic; verifying core-to-core timings and SoC level timing critical paths; and performing an overall design validation by using the silicon ICs and simulation testbenches of [an] the overall SoC [and application runs].

Abstract: Integrated circuit models having associated timing and tag information therewith for use with electronic design automation to effectively model timing exception information. The present invention includes a circuit block model which allows automated circuit optimization to be performed on extremely large circuits without the need to load all of the details of the circuit into computer memory. The circuit models of the present invention effectively model timing including timing exception information. The model of the present invention is associated with command information, e.g., textual commands, that describe tags (which model exceptions) and arrival and required times associated with the tags. Specifically, for the input pins of a circuit to be modeled, the present invention writes out a command defining each unique required tag associated with an input pin and also writes out commands associating each required tag with its input pin.

Abstract: A method is provided for compressing data. The method includes collecting data representative of a process. The method further includes scaling at least a portion of the collected data to generate mean values and mean-scaled values for the collected data. The method also includes calculating Scores from the mean-scaled values for the collected data using at most first, second, third and fourth Principal Components derived from a model using archived data sets and saving the Scores and the mean values.

Abstract: The invention concerns a system configuration setting method and a transmission apparatus, and simplifies system reconfiguration operations. The transmission apparatus comprises an HMI control block 1, a main control block 2, a line connection block 3, high-speed units 4 and 5, low-speed units 6 to 8, and a power supply unit 9, wherein the high-speed and low-speed units are managed by the main control block 2, whose management information is also stored in the HMI control block 1. A system reconfiguration command associated with a unit insertion, removal, etc. is entered into the transmission apparatus from a terminal 10.

Abstract: A process for efficiently computing moments in an interconnected circuit begins by partitioning the circuit into sets of line-like two-port circuits. Next, capacitors are converted to equivalent current sources and inductors are converted to equivalent voltage sources. From a first port, any connected voltage source which is present in line is added to the port voltage source. Then, that voltage source combined with the connected resistor and the Thevenin equivalent circuit is converted to a Norton equivalent circuit. The current source created from the conversion is added to a current source in the circuit and the Norton equivalent circuit is converted back to a Thevenin equivalent circuit. The process is recursively performed until the opposite port is reached. The moment is then computed from the final Thevenin equivalent circuit by using the voltage and current at the port. The Thevenin-Norton-Thevenin recursive process is then repeated for the opposite port.

Abstract: Method and apparatus for detecting and analyzing effects of noise in a digital circuit that arises from a coupling of signals produced by switching of a first gate and a second gate in a timed relationship. Where each of a first gate and a second gate can switch within a selected switching time interval, the gate switching effects are combined and the second gate output signal is analyzed with reference to the first gate input signal. Otherwise, the gate switching effects are not combined. When the second gate output signal satisfies at least one of three criteria, this condition is interpreted as indicating that the second gate permits propagation of a noise pulse produced at the first gate.

Abstract: An information processing system has first and second information processing apparatuses. The first information processing apparatus has an internal auxiliary storage device. The second information processing apparatus does not include an internal auxiliary storage device. Both information processing apparatuses have a main storage device, communication unit and auxiliary-storage-device control unit. The second information processing apparatus has an emulation mechanism for carrying out CKD-FBA format conversion to a series of CCW commands. Specifically, a command is set to access the internal auxiliary storage device and the emulation mechanism transmits the command set to the first information processing apparatus having the internal auxiliary storage device by way of the communication unit of the second information processing apparatus and a communication path.

Abstract: The present invention is directed to a peripheral device that integrally provides a program relating to the peripheral device, and may be connected to a computer system. The peripheral device includes a peripheral function subsystem for providing a peripheral device functionality. The peripheral device further includes a solid-state memory device storing a program relating to the peripheral device in a format used by disk drives. When the peripheral device is connected to a computer system, the program stored in the solid-state memory device is immediately available, and can be read by the computer system as though it was stored on a disk drive connected to the computer system.

Abstract: A system and method for facilitating configuration of client stations in a computer network. A virtual disk representing configuration information is formed and selectively exported via the network to the client stations. The stations are configured with the configuration information identified by the virtual disk. Snapshot disks representing modifications to the configuration information required at the client stations can also be created, transported across the computer network, and used to upgrade client station.

Abstract: The present invention provides a method and apparatus for performing automated development and updating of a manufacturing model for a manufacturing process. An initial manufacturing model is developed. Tolerances of the manufacturing model are expanded using additional production data. The manufacturing model is then re-developed using the expanded tolerances.

Abstract: To quickly determine a parting line, a mold design system first obtains the orientations of faces constituting an article to be produced using a mold, and then classifies the faces according to their orientations. A boundary between faces that are classified into different sets is determined as a parting line. Thus, the parting line is automatically determined, permitting efficient mold design.