Abstract: A metal oxide semiconductor transistor device having a reduced gate height is provided. One embodiment of the device includes a substrate having a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, and source/drain recesses formed in the semiconductor material adjacent to the gate structure, such that remaining semiconductor material is located below the source/drain recesses. The device also includes shallow source/drain implant regions formed in the remaining semiconductor material, and epitaxially grown, in situ doped, semiconductor material in the source/drain recesses.

Abstract: A trench DMOS transistor employing trench contacts has overvoltage protection for prevention of shortage between gate and source, comprising a plurality of first-type function trenched gates, at least one second-type function trenched gate and at least two third-type function trenched gates extending through body regions and into an epitaxial layer. The first-type function trenched gates are located in active area surrounded by a source region encompassed in the body region in the epitaxial layer for current conduction. The second-type function trenched gates are disposed underneath a gate metal with a gate trenched contacts filled with metal plug for gate metal connection. The third type function trenched gates are disposed directly and symmetrically underneath ESD trenched contact areas of anode and cathode in an ESD protection diode, serving as a buffer layer for prevention of gate-body shortage.

Abstract: An object is to provide a technique to manufacture an insulating film having excellent film characteristics. In particular, an object is to provide a technique to manufacture a dense insulating film with a high withstand voltage. Moreover, an object is to provide a technique to manufacture an insulating film with few electron traps. An insulating film including oxygen is subjected to plasma treatment using a high frequency under the conditions where the electron density is 1×1011 cm?3 or more and the electron temperature is 1.5 eV or less in an atmosphere including oxygen.

Abstract: A light emitting device includes a substrate, a first electrode layer, a light emitting layer, a structure layer and a second electrode layer. The structure layer has first domains composed of a first material having a columnar shape and second domains composed of a second material, and on the substrate the structure layer and the light emitting layer are laminated between the first electrode layer and the second electrode layer.

Abstract: An LED bare chip which is one type of a semiconductor light emitting device (2) includes a multilayer epitaxial structure (6) composed of a p-GaN layer (12), an InGaN/GaN MQW light emitting layer (14) and an n-GaN layer (16). A p-electrode (18) is formed on the p-GaN layer (12), and an n-electrode (20) is formed on the n-GaN layer (16). An Au plating layer (4) is formed on the p-electrode (18). The Au plating layer (4) supports the multilayer epitaxial structure (6) and conducts heat generated in the light emitting layer (14). The Au plating layer (4) is electrically divided into two portions by a polyimide member (10). One of the two portions (4A) is connected to the p-electrode (18), to be constituted as an anode power supply terminal, and the other portion (4K) is connected to the n-electrode (20) by a wiring (22), to be constituted as a cathode power supply terminal.

Abstract: A semiconductor device includes a semiconductor substrate, a first p-channel laterally diffused metal oxide semiconductor (LDMOS) transistor formed over the semiconductor substrate and additional p-channel LDMOS transistors formed over the semiconductor substrate. First drain and gate electrodes are formed over the substrate and are coupled to the first LDMOS transistor. Additional drain and gate electrodes are formed over the substrate and are coupled to the second LDMOS transistor. A common source electrode for the first and second LDMOS transistors is also formed over the substrate.

Abstract: A thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, and a gate electrode. The drain electrode is spaced from the source electrode. The semiconducting layer is electrically connected to the source electrode and the drain electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconducting layer by an insulating layer. The at least one of the source electrode, drain electrode, and the gate electrode includes a metallic carbon nanotube layer. The metallic carbon nanotube layer includes a plurality of metallic carbon nanotubes.

Abstract: Fabricating single-walled carbon nanotube transistor devices includes removing undesirable types of nanotubes. These undesirable types of nanotubes may include nonsemiconducting nanotubes, multiwalled nanotubes, and others. The undesirable nanotubes may be removed electrically using voltage or current, or a combination of these. This approach to removing undesirable nanotubes is sometimes referred to as “burn-off.” The undesirable nanotubes may be removed chemically or using radiation. The undesirable nanotubes of an integrated circuit may be removed in sections or one transistor (or a group of transistors) at a time in order to reduce the electrical current used or prevent damage to the integrated circuit during burn-off.

Abstract: A semiconductor light emitting diode includes a semiconductor substrate, an epitaxial layer of n-type Group III nitride on the substrate, a p-type epitaxial layer of Group III nitride on the n-type epitaxial layer and forming a p-n junction with the n-type layer, and a resistive gallium nitride region on the n-type epitaxial layer and adjacent the p-type epitaxial layer for electrically isolating portions of the p-n junction. A metal contact layer is formed on the p-type epitaxial layer. In method embodiments disclosed, the resistive gallium nitride border is formed by forming an implant mask on the p-type epitaxial region and implanting ions into portions of the p-type epitaxial region to render portions of the p-type epitaxial region semi-insulating. A photoresist mask or a sufficiently thick metal layer may be used as the implant mask.

Abstract: A solid-state image pickup device includes an element isolation insulating film electrically isolating pixels on the surface of a well region; a first isolation diffusion layer electrically isolating the pixels under the element isolation insulating film; and a second isolation diffusion layer electrically isolating the pixels under the first isolation diffusion layer, wherein a charge accumulation region is disposed in the well region surrounded by the first and second isolation diffusion layers, the inner peripheral part of the first isolation diffusion layer forms a projecting region, an impurity having a conductivity type of the first isolation diffusion layer and an impurity having a conductivity type of the charge accumulation region are mixed in the projecting region, and a part of the charge accumulation region between the charge accumulation region and the second isolation diffusion layer is abutted or close to the second isolation diffusion layer under the projecting region.

Abstract: A method of fabricating a pixel structure of a thin film transistor liquid crystal display is provided. A transparent conductive layer and a first metallic layer are sequentially formed over a substrate. The first metallic layer and the transparent conductive layer are patterned to form a gate pattern and a pixel electrode pattern. A gate insulating layer and a semiconductor layer are sequentially formed over the substrate. A patterning process is performed to remove the first metallic layer in the pixel electrode pattern while remaining the gate insulating layer and the semiconductor layer over the gate pattern. A second metallic layer is formed over the substrate. The second metallic layer is patterned to form a source/drain pattern over the semiconductor layer. A passivation layer is formed over the substrate and then the passivation layer is patterned to expose the transparent conductive layer in the pixel electrode pattern.

Abstract: The present invention relates to an LED package including a lead frame including a chip attaching portion with at least one LED chip attached thereto and a plurality of terminal portions each having a width narrower than the chip attaching portion, and a housing for supporting the lead frame. The plurality of terminal portions include at least one first terminal portion extending from a portion of a width of the chip attaching portion, and a plurality of second terminal portions spaced apart from the chip attaching portion.

Abstract: An Organic Light Emitting Display (OLED) and its method of fabrication, is capable of omitting a process of patterning a second pixel electrode by forming a first pixel electrode, forming a pixel-defining layer including an opening on the first pixel electrode, and forming the second pixel electrode and a third pixel electrode in the opening using a shadow mask as a mask. The OLED includes: a substrate; a first pixel electrode disposed on the substrate; a pixel-defining layer having an opening exposing a portion of the first pixel electrode; a second pixel electrode disposed on the first pixel electrode exposed by the opening of the pixel-defining layer and disposed in the opening of the pixel-defining layer; a third pixel electrode disposed on the second pixel electrode and disposed in the opening of the pixel-defining layer; an organic layer disposed on the third pixel electrode and including an emission layer; and an opposite electrode disposed on the organic layer.

Abstract: A semiconductor light emitting device includes a semiconductor layer having a recess extending downwardly from a top surface thereof along a pattern of a closed line so that said recess defines and encloses a region of the semiconductor layer that emits light, said semiconductor layer having a downward slope in at least a portion of its side end face located outside the closed line pattern of said recess; a first electrode on said downward slope of the side end face of the semiconductor layer and electrically in contact with a portion of said semiconductor layer, wherein said first electrode downwardly reflects light that is emitted by said semiconductor layer and that reaches the first electrode; and a second electrode electrically in contact with a portion of said semiconductor layer located inside the closed line pattern of said recess.

Abstract: Disclosed are embodiments of an n-FET structure with silicon carbon S/D regions completely contained inside amorphization regions and with a carbon-free gate electrode. Containing carbon within the amorphization regions, ensures that all of the carbon is substitutional following re-crystallization to maximize the tensile stress imparted on channel region. The gate stack is capped during carbon implantation so the risk of carbon entering the gate stack and degrading the conductivity of the gate polysilicon and/or damaging the gate oxide is essentially eliminated. Thus, the carbon implant regions can be formed deeper. Deeper S/D carbon implants which are completely amorphized and then re-crystallized provide greater tensile stress on the n-FET channel region to further optimize electron mobility. Additionally, the gate electrode is uncapped during the n-type dopant process, so the n-type dopant dose in the gate electrode can be at least great as the dose in the S/D regions.

Abstract: A display substrate includes a gate electrode, a gate insulating layer, and a semiconductor layer that are sequentially formed on a substrate. Also, the display substrate includes a color filter layer formed on the substrate and exposing a portion of the semiconductor layer, and source and drain electrodes that each overlap with the semiconductor layer and the color filter layer. The gate electrode, the gate insulating layer, and the semiconductor layer have the same shape as each other, and the gate electrode is insulated from the gate insulating layer and the semiconductor layer by the color filter layer.

Abstract: A semiconductor device includes a first circuit substrate having a plurality of lower wiring lines and a plurality of upper wiring lines on the lower surface side and upper surface side thereof, respectively. A second circuit substrate is provided on a lower side of the first circuit substrate, the second circuit substrate having an opening which exposes part of the first circuit substrate, the second circuit substrate also having, on the lower surface side thereof, a plurality of external-connection connection pads and a plurality of test connection pads connected to the lower wiring lines. A first semiconductor construct is disposed on the lower side of the first circuit substrate within the opening of the second circuit substrate, the first semiconductor construct having a plurality of external connection electrodes connected to the lower wiring lines.

Abstract: The present invention generally relates to the fabrication of molecular electronics devices from molecular wires and Single Wall Nanotubes (SWNT). In one embodiment, the cutting of a SWNT is achieved by opening a window of small width by lithography patterning of a protective layer on top of the SWNT, followed by applying an oxygen plasma to the exposed SWNT portion. In another embodiment, the gap of a cut SWNT is reconnected by one or more difunctional molecules having appropriate lengths reacting to the functional groups on the cut SWNT ends to form covalent bonds. In another embodiment, the gap of a cut SWNT gap is filled with a self-assembled monolayer from derivatives of novel contorted hexabenzocoranenes. In yet another embodiment, a device based on molecular wire reconnecting a cut SWNT is used as a sensor to detect a biological binding event.

Abstract: To provide a flip-chip mounting method and a bump formation method applicable to flip-chip mounting of a next generation LSI and having high productivity and high reliability. A semiconductor chip 20 having a plurality of electrode terminals 12 is held to oppose a circuit board 21 having a plurality of connection terminals 11 with a given gap provided therebetween, and the semiconductor chip 20 and the circuit board 21 in this state are dipped in a dipping bath 40 containing a melted resin 14 including melted solder particles for a given period of time. In this dipping process, the melted solder particles self-assemble between the connection terminals 11 of the circuit board 21 and the electrode terminals 12 of the semiconductor chip 20, so as to form connectors 22 between these terminals.

Abstract: The present invention relates generally to assembly techniques. According to the present invention, the alignment and probing techniques to improve the accuracy of component placement in assembly are described. More particularly, the invention includes methods and structures to detect and improve the component placement accuracy on a target platform by incorporating alignment marks on component and reference marks on target platform under various probing techniques. A set of sensors grouped in any array to form a multiple-sensor probe can detect the deviation of displaced components in assembly.