Patents Examined by Wai-Sing Louie
  • Patent number: 8049239
    Abstract: Provided are a light emitting device and a method of manufacturing the same. A light emitting device includes an active layer; a first conductive semiconductor layer on the active layer; a second conductive semiconductor layer on the active layer so that the active layer is disposed between the first and second conductive semiconductor layers; and a photonic crystal structure comprising a first light extraction pattern on the first conductive semiconductor layer having a first period, and second light extraction pattern on the first conductive semiconductor layer having a second period, the first period being greater than ?/n, and the second period being identical to or smaller than ?/n, where n is a refractive index of the first conductive semiconductor layer, and ? is a wavelength of light emitted from the active layer.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: November 1, 2011
    Assignee: LG Innotek Co., Ltd.
    Inventors: Sun Kyung Kim, Jin Wook Lee, Hyun Kyong Cho
  • Patent number: 8048794
    Abstract: A method of fabricating a thin wafer die includes creating circuits and front-end-of-line wiring on a silicon wafer, drilling holes in a topside of the wafer, depositing an insulator on the drilled holes surface to provide a dielectric insulator, removing any excess surface deposition from the surface, putting a metal fill into the holes to form through-silicon-vias (TSV), creating back-end-of-line wiring and pads on the top surface for interconnection, thinning down the wafer to expose the insulator in from the TSVs to adapt the TSVs to be contacted from a backside of the wafer, depositing an insulating layer which contacts the TSV dielectric, thinning down the backside of the wafer, opening through the dielectric to expose the conductor of the TSV to provide a dielectric insulation about exposed backside silicon, and depositing ball limiting metallurgy pads and solder bumps on the backside of the wafer to form an integrated circuit.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: November 1, 2011
    Assignee: International Business Machines Corporation
    Inventor: John U. Knickerbocker
  • Patent number: 8049237
    Abstract: A light emitting device includes a substrate provided with a conductor wiring, a light emitting element mounted on the substrate and a light reflecting resin member configured and arranged to reflect light emitted from the light emitting element. The light emitting device also includes at least one of an electrically conductive wire electrically connecting the conductor wiring and the light emitting element, an exposed region of the substrate on which the conductor wiring is not disposed, and a protective element mounted on the conductor wiring. At least a part of the electrically conductive wire, the exposed region or the protective element is buried in the light reflecting resin member.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: November 1, 2011
    Assignee: Nichia Corporation
    Inventors: Motokazu Yamada, Mototaka Inobe
  • Patent number: 8048710
    Abstract: A photoelectric conversion device according to the present invention has a plurality of photoreceiving portions provided in a substrate, an interlayer film overlying the photoreceiving portion, a large refractive index region which is provided so as to correspond to the photoreceiving portion and has a higher refractive index than the interlayer film, and a layer which is provided in between the photoreceiving portion and the large refractive index region, and has a lower etching rate than the interlayer film, wherein the layer of the lower etching rate is formed so as to cover at least the whole surface of the photoreceiving portion. In addition, the layer of the lower etching rate has a refractive index in between the refractive indices of the large refractive index region and the substrate. Such a configuration can provide the photoelectric conversion device which inhibits the lowering of the sensitivity and the variation of the sensitivity among picture elements.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: November 1, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventor: Sakae Hashimoto
  • Patent number: 8049210
    Abstract: Provided is a thin film transistor including a substrate, a source electrode and a drain electrode disposed above the substrate so as to oppose each other, an organic semiconductor film disposed between the source electrode and the drain electrode to generate a channel region, and a gate electrode disposed opposite the organic semiconductor film via a gate insulating film. The gate electrode includes an aperture in the channel region.
    Type: Grant
    Filed: January 20, 2009
    Date of Patent: November 1, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Takashi Aoki, Soichi Moriya
  • Patent number: 8044501
    Abstract: A contact that takes a structure to laminate a protective conductive film over a metal film has a high hardness of the protective conductive film; therefore, a damage of contact surface made by contacting with an electrode of an inspection apparatus can be prevented in an inspection before boding FPC. However, the protective conductive film has higher resistivity compared to the metal film; therefore, contact resistivity with FPC gets higher, and power consumption gets bigger in the condition of using the display device.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: October 25, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hideyuki Ebine
  • Patent number: 8044467
    Abstract: A semiconductor device with reduced contact resistance between a substrate and a plug includes a gate electrode disposed over the substrate, the plug formed over the substrate at both sides of the gate electrode and having a sidewall with a positive slope, a capping layer disposed between the gate electrode and the plug, and a gate hard mask layer whose sidewall disposed over the gate electrode is extended to a top surface of the capping layer. By employing the capping layer having a sidewall with a negative slope, the plug having the sidewall with a positive slope can be formed regardless of a shape or profile of the sidewall of the gate electrode. As a result, the contact area between the substrate and the plug is increased.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: October 25, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Byung-Duk Lee
  • Patent number: 8044419
    Abstract: Phosphor compositions, white phosphor compositions, methods of making white phosphor compositions, tinted white phosphor compositions, methods of making tinted white phosphor compositions, LEDs, methods of making LEDs, light bulb structures, paints including phosphor compositions, polymer compositions including phosphor compositions, ceramics including phosphor compositions, and the like are provided.
    Type: Grant
    Filed: May 21, 2007
    Date of Patent: October 25, 2011
    Assignee: University of Georgia Research Foundation, Inc.
    Inventors: William M. Yen, Zhiyi He, Sergei Basun, Xiao-jun Wang, Gennaro J. Gama
  • Patent number: 8044420
    Abstract: The present invention relates to a method for forming a package structure for a light emitting diode (LED) and the LED package structure thereof. By employing the same sawing process to cut through the trenches of the leadframe, the package units are singulated and different lead portions are simultaneously separated from each other in each package unit. Therefore, the overflow issues of the encapsulant can be avoided without using extra taping process.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: October 25, 2011
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Seongoo Lee, Ryungshik Park, Hyunil Lee, Hyunsoo Jeong
  • Patent number: 8044388
    Abstract: Manufacturers encounter limitations in forming low resistance ohmic electrical contact to semiconductor material P-type Gallium Nitride (p-GaN), commonly used in photonic applications, such that the contact is highly transparent to the light emission of the device. Carbon nanotubes (CNTs) can address this problem due to their combined metallic and semiconducting characteristics in conjunction with the fact that a fabric of CNTs has high optical transparency. The physical structure of the contact scheme is broken down into three components, a) the GaN, b) an interface material and c) the metallic conductor. The role of the interface material is to make suitable contact to both the GaN and the metal so that the GaN, in turn, will make good electrical contact to the metallic conductor that interfaces the device to external circuitry. A method of fabricating contact to GaN using CNTs and metal while maintaining protection of the GaN surface is provided.
    Type: Grant
    Filed: July 21, 2009
    Date of Patent: October 25, 2011
    Assignee: Nantero, Inc.
    Inventors: Jonathan W. Ward, Benjamin Schlatka, Mitchell Meinhold, Robert F. Smith, Brent M. Segal
  • Patent number: 8039351
    Abstract: A method of fabricating a hetero-junction bipolar transistor (HBT) is disclosed, where the HBT has a structure incorporating a hetero-junction bipolar structure disposed on a substrate including of silicon crystalline orientation <110>. The hetero-junction bipolar structure may include an emitter, a base and a collector. The substrate may include a shallow-trench-isolation (STI) region and a deep trench region on which the collector is disposed. The substrate may include of a region of silicon crystalline orientation <100> in addition to silicon crystalline orientation <110> to form a composite substrate by using hybrid orientation technology (HOT). The region of crystalline orientation <100> may be disposed on crystalline orientation <110>. Alternatively, the region of silicon crystalline orientation <110> may be disposed on crystalline orientation <100>.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: October 18, 2011
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, Rajendran Krishnasamy
  • Patent number: 8039862
    Abstract: A white light emitting diode (LED) package with multilayered encapsulation structure and the packaging methods are disclosed. The white LED package structure includes metal electrodes, a heat dissipation base, a PPA plastic for fixing the electrodes and the heat dissipation base together, at least one LED die, a die attaching material, gold wires for electrically connecting the LED die to the electrodes, a first type of silicone encapsulant, a second type of silicone encapsulant, and a phosphor containing layer. The invention utilizes a low-refractive index silicone (the second type of silicone encapsulant) to separate the phosphor containing layer away from the first type of silicone, which covers the LED die, to prevent/reduce emitted light going backward and hitting the LED die.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: October 18, 2011
    Assignee: Nepes LED Corporation
    Inventors: Nguyen The Tran, Yungzhi He, Frank Shi
  • Patent number: 8039970
    Abstract: A stacked semiconductor device includes a first semiconductor element mounted on a circuit substrate and a second semiconductor element stacked on the first semiconductor element via a spacer layer. An electrode pad of the first semiconductor element is electrically connected to a connection portion of the circuit substrate through a first metal wire. A vicinity of the end portion of the first metal wire connected to the electrode pad is in contact with an insulating protection film which covers the surface of the first semiconductor element.
    Type: Grant
    Filed: January 29, 2008
    Date of Patent: October 18, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiro Yamamori, Katsuhiro Ishida
  • Patent number: 8039280
    Abstract: The present invention provides a method of fabricating a light emitting diode, which comprises the steps of forming a compound semiconductor layer on a substrate, the compound semiconductor layer including a lower semiconductor layer, an active layer and an upper semiconductor layer; and scratching a surface of the substrate by rubbing the substrate with an abrasive. According to the present invention, the abrasive is used to rub and scratch the surface of the light emitting diode, thereby making it possible to cause the light emitted from the active layer to effectively exit to the outside. Therefore, the light extraction efficiency of the light emitting diode can be improved.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: October 18, 2011
    Assignees: Seoul Opto Device Co., Ltd., The University of Tokushima
    Inventors: Shiro Sakai, Yoshiki Naoi
  • Patent number: 8036399
    Abstract: An audio output apparatus includes: an audio codec outputting an analog audio signal corresponding to a digital audio signal from a system controller; a switch unit having a first end coupled to the audio codec through a capacitor, and a grounded second end; and a switch controller triggered by a trigger signal to output a control signal to a control end of the switch unit such that the switch unit couples the capacitor to ground in response to the control signal. The trigger signal is generated by one of the system controller, the audio codec, and a power circuit supplying electric power to the system controller, the audio codec and the switch controller upon occurrence of a condition associated with pop noise, and is outputted to the switch controller before the pop noise is generated, such that the pop noise is conducted to ground via the switch unit.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: October 11, 2011
    Assignee: Twinhead International Corporation
    Inventors: Chun-Chen Chao, Li-Chang Lai, Shih-Yuan Chang
  • Patent number: 8035202
    Abstract: A semiconductor chip of the present invention has a wiring substrate and a chip part. The wiring substrate has an insulating resin layer having a first major surface and a second major surface, and a first wiring layer disposed on the insulating resin layer on the second major surface side. The chip part has a projection electrode on the bottom surface. The insulating resin layer holds the chip part such that the bottom and side surfaces of the chip part are in contact with the insulating resin layer, and the top surface of the chip part is exposed on the insulating layer on the first major surface side. The projection electrode of the chip part is connected with the first wiring layer.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: October 11, 2011
    Assignee: NEC Corporation
    Inventors: Shinji Watanabe, Yukio Yamaguchi
  • Patent number: 8030681
    Abstract: A group III nitride substrate in one embodiment has a surface layer. The surface layer contains 3 at. % to 25 at. % of carbon and 5×1010 atoms/cm2 to 200×1010 atoms/cm2 of a p-type metal element. The group III nitride substrate has a stable surface.
    Type: Grant
    Filed: January 19, 2009
    Date of Patent: October 4, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Keiji Ishibashi
  • Patent number: 8030692
    Abstract: A solid state image sensing device in which many pixels are disposed in a matrix on a two-dimensional plane comprises a plurality of light receiving devices disposed in such a way that a center interval may periodically change in a column direction and/or a row direction, and a plurality of micro-lenses, for collecting an incident light of each light receiving device, wherein a center interval periodically changes in accordance with the periodic change of the center interval of the light receiving device.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: October 4, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Tadao Inoue, Hiroshi Daiku
  • Patent number: 8030745
    Abstract: The present invention provides an ID chip or an IC card in which the mechanical strength of an integrated circuit can be enhanced without suppressing a circuit scale. An ID chip or an IC card of the present invention has an integrated circuit in which a TFT (a thin film transistor) is formed from an insulated thin semiconductor film. Further, an ID chip or an IC card of the present invention has a light-emitting element and a light-receiving element each using a non-single-crystal thin film for a layer conducting photoelectric conversion. Such a light-emitting element or a light-receiving element may be formed consecutively to (integrally with) an integrated circuit or may be formed separately and attached to an integrated circuit.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: October 4, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8030108
    Abstract: Exemplary embodiments provide semiconductor nanowires and nanowire devices/applications and methods for their formation. In embodiments, in-plane nanowires can be epitaxially grown on a patterned substrate, which are more favorable than vertical ones for device processing and three-dimensional (3D) integrated circuits. In embodiments, the in-plane nanowire can be formed by selective epitaxy utilizing lateral overgrowth and faceting of an epilayer initially grown in a one-dimensional (1D) nanoscale opening. In embodiments, optical, electrical, and thermal connections can be established and controlled between the nanowire, the substrate, and additional electrical or optical components for better device and system performance.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: October 4, 2011
    Assignee: STC.UNM
    Inventors: Seung Chang Lee, Steven R. J. Brueck