Abstract: Provided is an apparatus and method for routing communications in an Advanced Intelligent Network (AIN) having at least one central office switch. The disclosed system routes communications from a calling party having at least one Customer Premises Equipment (CPE) device to a secondary party having a single calling number for a plurality of CPE devices, each having a corresponding communication address. In operation, communications are routed to a central office switch which is provided in electrical communication with at least one adjunct processor. Thereafter, the desired type of secondary CPE device sought to be accessed is identified in cooperation with storage means which is provided in electrical communication with the adjunct processor. As disclosed, the storage means is provided for storing a directory having a plurality of secondary party calling numbers and corresponding communication addresses.

Abstract: This invention is a technique for summing plural sections of a single data word. The technique uses a repeated process forming larger and larger partial sums. Initially the single data word is rotated one section. The original single data word and the rotated single data word are masked with a mask having "1's" and "0's" in alternate sections. The mask blocks alternate sections so that adjacent sections of the original data word may be summed on a whole data word basis without any overflow disrupting the partial products. The two masked data words are then summed. This sum results in half as many partial sums as before. Each of these larger partial sums now occupies two original sections of the data word. The process can be repeated for these large partial sums. In the preferred embodiment this technique is used with an arithmetic logic unit (230) capable of forming mixed arithmetic and Boolean combinations of three inputs having a barrel rotator (235) driving one input.

Abstract: A single-chip microcomputer is constituted by a single-chip microcomputer core, an external bus interface circuit, an external bus, a logic circuit and a bus interface. For asynchronously accessing to an exterior from the single-chip microcomputer core, the external bus interface circuit produces an asynchronous access control signal to the exterior based on an access control signal from the single-chip microcomputer core. The internal bus interconnects the single-chip microcomputer core and the external bus interface circuit, and the logic circuit is asynchronously accessible to and from the single-chip microcomputer core. The bus interface circuit is connected to the internal bus and produces an asynchronous access control signal to the logic circuit based on an access control signal inputted through the internal bus.

Abstract: A switching state detecting apparatus capable of preventing output voltage hunting caused by mechanical switch contacts bouncing when changing state and creating voltage fluctuation (chatter) comprises a passive filter connected to the switches and a comparator for comparing the output value of the RC filter with a threshold level to then output a voltage value. The comparator changes the threshold level when the output voltage of the comparator is inverted, thereby preventing the apparatus from hunting. The output of the comparator is potentially divided and the divided output potential is superposed onto an initial threshold level to provide a second threshold level exceeding the voltage chatter level of said switches.

Abstract: In a milli-mode processor, bits (0-6) of an access list entry token (ALET) in the program access register must be zeros in order for access register translation to be successful. When the ALET is being copied from a program access register to a millicode access register, bits 0-3 of ALET, written into the millicode access register, are set to the access register number of the program access register from which the data is being read. This establishes the affinity between the program access register number and any logical fetches which might be attempted by millicode.

Abstract: A coprocessor has a systolic array of processors each associated with a memory; an array data bus conveying input data to and output data from connections to the array; data buffers for the input and output data; an input and output data bus communicating with the data buffers and with a host processor; a control bus conveying successive operation codes to the array processors an instruction control store containing instructions providing operation codes for successive operations of the array processors, and a sequencer to select instructions from the control store. An intermediate data bus with a microprocessor and further random access memory communicating with that bus, carries input and output data for the array, input and output data for the microprocessor, and addresses for the memories associated with the processors of the array and for the sequencer.

Abstract: A dual bus architecture for a computer system including a number of computer system devices and a number of computer system resources. Each of the computer system devices and computer system resources are coupled by first and second communication busses. First and second bus arbitrators provide bus arbitration functions allowing first and second computer system devices to access first and second computer system resources simultaneously. A method of accessing a number of computer system resources by a number of computer system devices coupled by a dual bus architecture is also provided.

Abstract: To connect the various stations of a data processing system, a bus system is used, to which all users have access. In accordance with the invention, a method for automatic assignment of bus addresses is provided, whereby each user generates a random address that is enquired by a control unit. After clashes recognized by the control unit, this method is repeated until each user has been assigned a clear address.

Abstract: A new system and method allows a Manager in a Simple Network Management Protocol (SNMP) environment to gather updates from its Agents. The system and method comprise the unique provision of an index which is used in each of the Agent's tables for indicating the various revisions thereof. The index lexicographically increases with each revision to the table. The Manager maintains a record of the index of the data which it has received from its Agents, requesting only that data having a lexicographically larger indexing. Further, the index is used in related tables so that the tables will be kept in "sync" in that the Manager will know whether it has the latest updates so that an accurate picture may be portrayed.

Abstract: A modular array processor architecture (10) comprising a plurality of interconnected parallel processing node (11)s that each comprise a control processor (12), an arithmetic processor (13) having an input port (22) for receiving data from an external source that is to be processed, a node memory (14) that also comprises a portion of a distributed global memory, and a network interface (15) coupled between the control processor (12), the arithmetic processor (13), and the node memory (14). Data and control buses (17, 18) are coupled between the arithmetic processors (13) and network interfaces (14) of each of the processing nodes (11). Respective network interfaces (15) link each of the arithmetic processors (13), node memories (14) and control processors (12) together to provide for communication throughout the architecture (10) and permit each node to communicate with the node memories (14) of all other processing nodes (11).

Abstract: This invention involves computing a mean squared error between a predetermined plural number of pairs of first and second values. A data processing apparatus (71, 72, 73, 74) has data registers (200), an arithmetic logic unit (230), a flags register (211), a multiplication unit (220), a source of instructions and an instruction decoder (245, 246, 250). The arithmetic logic unit (230) forms a difference between pairs. The flags register (211) stores status bits indicating whether the result is less than zero. The arithmetic logic unit (230) conditionally either adds the difference to zero if the status bit indicates the difference was not less than zero or subtracts the difference from zero if the status bit indicated the difference was less than zero. The multiplication unit (220) forms the square. The square is added to a running sum.

Abstract: Fault tolerant topology for passive optical networks essentially based on a "tree configuration" with branch points or nodes (16, 17) made up of passive optical splitters, in which each node (16, 17) of a specific level is connected to the same number of nodes (16, 17) of the level immediately below by two or more branches (Rd, Rs) and a supplementary connection (S1, S2 . . . ) is provided between each pair of nodes of the same level (FIG. 1).

Abstract: Modular, portable data collection terminals are disclosed for use in mixed wireless and hard-wired RF communication networks, wherein various radio transmitter modules and associated antennas may be selectively added to a base terminal unit to solve networking problems associated with specific types of business environments. Modularity exists in both the hardware (splitting data collection and processing control circuitry from radio transceiver control circuitry) and software (splitting transceiver-specific, lower level communication protocol from generic, higher level communication protocol). The control circuitry, including associated microprocessors devices, interact to selectively activate communication circuits to perform necessary communication or data processing functions and enter and remain in a power-saving dormant state during other times. To support such dormant or "sleeping" states, a series of communication protocols provide for channel access to the communication network.

Abstract: A personal computer's microprocessor is time-shared to provide the functions formerly provided by a microprocessor dedicated to a modem. This technique is transparent to software applications programs which interact with a modem. The personal computer utilizes an operating system, such as the Microsoft Windows operating system, in which a portion of the operating system, known as the communications driver, provides the interface between the operating system and the personal computer's serial and parallel communication ports. All communications between the communications driver and the rest of the operating system are examined. Those communications destined for a particular port associated with a modem not having a dedicated microprocessor are redirected while other communications destined for other ports are passed to the Microsoft Windows communications driver.

Abstract: A system for interconnecting line cards attached to a networking hub is disclosed. The disclosed system operates by forming backplane networks between the line cards using shared data path resources within the hub. Each line card attached with the hub describes its hub internal networking characteristics and capabilities. A hub management agent obtains the specific capabilities and characteristics of each line card attached to the networking hub, from each of the line cards. The characteristics and capabilities of each line card include which of the shared data path resources are accessible to the line card, and how the line card is able to operate on those accessible shared data path resources. The capabilities and characteristics of the line cards are obtained by the management agent requesting each line card for the information. The request is initiated by a triggering event, for example power-up of the networking hub or attachment of a new line card to the networking hub.

Abstract: A computer program architecture for a motor vehicle on-board diagnostic system includes a plurality of monitor modules for monitoring vehicle systems or components and issuing a malfunction subroutine call to a diagnostic executive upon detecting a system or component malfunction. The executive includes a plurality of software objects or modules for carrying out malfunction indicator light control and fault code storage strategies. A diagnostic scheduler module implemented as a finite state machine, controls and coordinates the sequence of the test to be run by the monitor modules as well as on-demand self tests. A malfunction indicator light (MIL) control module implements four distinct light control strategies through finite machines for illuminating and extinguishing the light and for storing and erasing fault codes under predetermined conditions.

Abstract: In a computer system, a direct access, independently arbitrated video bus (connected to a personal computer (PC) -compatible video subsystem) is directly coupled to one or more dual-ported processors to eliminate video cycle traffic over the system bus or buses and I/O bus, thereby improving system performance. The preferred embodiment architecture has, in addition to the video bus, multiple processors coupled to at least two independently arbitrated system buses which are coupled to at least two independently arbitrated input/output (I/O) buses, to provide for rapid bus information signal transfer rates.

Abstract: A pipelined SIMD-systolic array processor and its methods, mainly comprising a number of processing elements constructed as array architecture, multiport memory, registers, multiplexers, and controller, wherein the registers and multiplexers are connected for transferring data between the multiport memory and processing elements, the methods thereof uses a way which combines both broadcasting and systolic structures for transferring data into and out each processing element, and moreover, the method uses the controller to manipulate data transferring and the operation of each processing element for various functions; the array processor can have a faster processing speed and, through using a multiport memory, each processing element requires only a small amount of storage, and therefore, the array processor can use memory in a more efficient way.

Abstract: A single-instruction multiple-data processor (10) has an input layer especially designed for high data input and output rates. The processor (10) has a number of processing elements (20), each corresponding to incoming data samples. The processing elements (20) are interleaved so that a set of samples can be input in parallel. This configuration permits the processor to achieve a higher data input rate.

Abstract: A processing system and method of operation are provided. At least one execution unit processes information of a register in response to an instruction specifying the register. Each of multiple control units selectively allocates a respective one of multiple buffers to store the information in response to the instruction.