Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises: a semiconductor layer; a first gate insulating film; a plurality of floating gate electrodes; a second gate insulating film; a plurality of control gate electrodes; and an upper insulating film. The semiconductor layer is provided on a substrate and extends in a first direction. The floating gate electrode is formed on the semiconductor layer via the first gate insulating film. The control gate electrode faces the upper surface of the floating gate electrode via the second gate insulating film. Moreover, the control gate electrode extends in a second direction intersecting the first direction. The upper insulating film is formed on an upper portion of the plurality of control gate electrodes. Moreover, a height of an upper surface of the upper insulating film changes along the second direction.

Abstract: A semiconductor device includes a device isolation region defining an active region in a substrate, and gate structures buried in the active region of the substrate. At least one of the gate structures includes a gate trench, a gate insulating layer conformally formed on an inner wall of the gate trench, a gate barrier pattern conformally formed on the gate insulating layer disposed on a lower portion of the gate trench, a gate electrode pattern formed on the gate barrier pattern and filling the lower portion of the gate trench, an electrode protection layer conformally formed on the gate insulating layer disposed on an upper portion of the gate trench to be in contact with the gate barrier pattern and the gate electrode pattern, a buffer oxide layer conformally formed on the electrode protection layer, and a gate capping insulating layer formed on the buffer oxide layer to fill the upper portion of the gate trench.

Abstract: The present invention provides a thin film transistor, an array substrate and a display device, relating to the field of display technology, for solving the problem that a source/drain electrode metals and a gate metal may be short-circuited in the manufacturing process of an existing bottom-gate thin film transistor. The thin film transistor of the present invention comprises: a gate formed on a substrate, the gate being connected with a gate line; and a semiconductor layer formed on the gate and the gate line, at least a part of the semiconductor layer extends in the direction parallel to the substrate to exceed the edge of the gate. The array substrate of the present invention comprises the thin film transistor, and the display device comprises the array substrate. The present invention may improve the yield of the bottom-gate thin film transistor.

Abstract: The present disclosure relates to a semiconductor device substrate and a method for making the same. The semiconductor device substrate includes a first dielectric layer, a second dielectric layer and an electronic component. The first dielectric layer includes a body portion, and a wall portion protruded from a first surface of the body portion. The wall portion has an end. The second dielectric layer has a first surface and an opposing second surface. The first surface of the second dielectric layer is adjacent to the first surface of the body portion. The second dielectric layer surrounds the wall portion. The end of the wall portion extends beyond the second surface of the second dielectric layer. The electronic component includes a first electrical contact and a second electrical contact. At least a part of the electronic component is surrounded by the wall portion.

Abstract: An image sensor includes: a first inter-layer dielectric layer formed over a front side of a substrate including photoelectric conversion regions; isolation structures each of which penetrates through the first inter-layer dielectric layer and has a portion buried in the substrate; first metal lines formed over the first inter-layer dielectric layer to correspond to the photoelectric conversion regions; and an optical filter and a light condenser formed over a back side of the substrate.

Abstract: A diode is integrated on a semiconductor chip having anode and cathode surfaces opposite to each other. The diode comprises a cathode region extending inwardly from the cathode surface, a drift region extending between the anode surface and the cathode region, and a plurality of anode regions extending from the anode surface in the drift region. The diode further comprises a cathode electrode coupled with the cathode region, and an anode electrode that contacts one or more contacted anode regions of said anode regions and is electrically insulated from one or more floating anode regions of the anode regions. The diode is configured so that charge carriers are injected from the floating anode regions into the drift region in response to applying of a control voltage exceeding a threshold voltage.

Abstract: Forming a semiconductor arrangement includes non-destructively determining a first spacer height of a first sidewall spacer adjacent a dummy gate and a second spacer height of a second sidewall spacer adjacent the dummy gate based upon a height of a photoresist as measured using optical critical dimension (OCD) spectroscopy. When the photoresist is sufficiently uniform, a hard mask etch is performed to remove a hard mask from the dummy gate and to remove portions of sidewall spacers of the dummy gate. A gate electrode is formed between the first sidewall spacer and the second sidewall spacer to form a substantially uniform gate. Controlling gate formation based upon photoresist height as measured by OCD spectroscopy provides a non-destructive manner of promoting uniformity.

Abstract: A circuit device mounted on a substrate includes a detection circuit that monitors a characteristic of a return signal to determine an integrity of various interconnects of the device.

Abstract: The invention proposes a semiconductor device package structure, comprising a substrate, an adhesive layer and a die. The substrate has electrical through-holes to inter-connect a first and second wiring circuit on a top surface and a bottom surface of the substrate respectively, wherein a contact conductive bump is formed on the first wiring circuit. The under-fill adhesive layer is formed on the top surface and the first wiring circuit of the substrate except the area of the die. The die has a bump structure on the bonding pads of the die, wherein the bump structure of the die is electrically connected to the contact conductive bump of the first wiring circuit of the substrate.

Abstract: A method for manufacturing a micromechanical component includes the following sequential steps: a first material layer including a first joining partner being applied to a first wafer; a second material layer including a second joining partner being applied to a second wafer; a micromechanical structure being created in the first wafer by gas phase etching with the aid of a gaseous etching medium which is applied to the first joining partner; the first and second wafers being joined in such a way that they are in contact at least in some areas; and the first and second joining partners being heated to be integrally joined to form a connecting layer, a eutectic joining material being formed in the connecting layer from the first joining partner and the second joining partner.

Abstract: A memory device, and a method of making the memory device, are disclosed. The memory device is fabricated by mounting one or more semiconductor die on a substrate, and wire bonding the die to the substrate. The die and wire bonds are encapsuated, and the encapsulated device is singulated. The wire bonds are severed during the singulation step, and thereafter the severed wire bonds are connected to the substrate by external connectors on one or more surfaces of the molding compound.

Abstract: A nonvolatile semiconductor memory according to an embodiment includes: a semiconductor region; a first insulating film formed on the semiconductor region; a charge storage film formed on the first insulating film; a hydrogen diffusion preventing film formed on the charge storage film; a second insulating film formed on the hydrogen diffusion preventing film; a control gate electrode formed on the second insulating film; a hydrogen discharge film formed on the control gate electrode; and a sidewall formed on a side surface of a multilayer structure including the first insulating film, the charge storage film, the hydrogen diffusion preventing film, the second insulating film, and the control gate electrode, the sidewall containing a material for preventing hydrogen from diffusing.

Abstract: In one embodiment, a method for forming a magnetoresistive read head includes forming a fixed layer having a first ferromagnetic material that has a fixed direction of magnetization above a lower shield layer, forming a free layer having a second ferromagnetic material positioned above the fixed layer, the free layer having a non-fixed direction of magnetization, forming a first mask above the free layer, the first mask having a predetermined width based on a track width of a magnetic medium, etching the free layer down to the fixed layer using the first mask as a guide, wherein substantially none of the fixed layer is etched, and wherein the fixed layer extends beyond both sides of the free layer in a cross-track direction, and forming magnetic domain control films on both sides of the free layer in the cross-track direction, the magnetic domain control films including a soft magnetic material.

Abstract: The present disclosure provides an interconnect structure, including a substrate, a first conductive feature over the substrate, a second conductive feature over the first conductive feature, and a dielectric layer surrounding the first conductive feature and the second conductive feature. A width of the first conductive feature and a width of the second conductive feature are between 10 nm and 50 nm. The present disclosure also provides a method for manufacturing an interconnect structure, including (1) forming a via opening and a line trench in a dielectric layer, (2) forming a 1-dimensional conductive feature in the via opening, (3) forming a conformal catalyst layer over a sidewall of the line trench, a bottom of the line trench, and a top of the 1-dimensional conductive feature, and (4) removing the conformal catalyst layer from the bottom of the line trench and the top of the 1-dimensional conductive feature.

Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side.

Abstract: Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.

Abstract: A lead frame assembly which allows for the connection of multiple individual fixed components in various locations, while alleviating tolerance concerns by having a flexible lead frame. The lead frame assembly includes several sub-lead frames, and a plurality of interconnects which connect each of the sub-lead frames together. The lead frame assembly also includes a plurality of segments, and each segment surrounds one of the sub-lead frames, to electrically isolate each sub-lead frame. Various components are electrically connected by incorporating stamped receptacles, or slot terminals, in the sub-lead frames. The interconnects along with plastic voids allow the various attached components to have tolerance flexibility relative to one another, as various components are attached to each of the slot terminals.

Abstract: A semiconductor apparatus includes a first power supply pad configured to supply a first power; a second power supply pad configured to supply a second power; a first power line configured to be directly electrically coupled to the first power supply pad; and a second power line configured to be directly electrically coupled to the second power supply pad.

Abstract: A white organic light emitting element, a white organic light emitting display device, and a method of manufacturing the white organic light emitting element are provided. The organic light emitting element includes a multi-layered emission layer structure. The multi-layered emission layer structure includes a first electroluminescent layer and a second electroluminescent layer that are arranged to overlap at first area of the white organic light emitting element. The lights from the first and second electroluminescent layers collectively form white light. Among the first and second electroluminescent layers, one of the EL layers is extended out to the second area of the white organic light emitting element. A plurality of color filter elements are used to filter the white light to generate colored lights at the corresponding sub pixel regions.

Abstract: A sensor device has a substrate, a sensor section provided on an upper surface of the substrate, a circuit section provided on the upper surface of the substrate, a plurality of connection pads that electrically conduct with the sensor section or the circuit section, and a metal protective film covering at least a part of the circuit section from above.